No FEC in the CyFi?

[Anonymous]

        From the scarce information provided about the Phy of CY3271 modem I could not find any mention to a forward error correction (FEC) scheme, which is almost always used in digital wireless schemes, e.g.convolutional encoding -> Interleaver -> Deinterleaver -> Viterbi decoding. Is it the case that the Phy only relies on the spreading gain provided by the DSSS scheme and power level control to overcome the inevitable channel errors?   
   
I understand that the simpler the Phy (and the upper level protocol) the more power efficient the chip will be, also it might be the case that the packets are short (5 bytes maximum?) so for the same SNR they are less prone to be in error than a longer packet. Anyway, this looks like an interesting chip/kit.   

[Anonymous]

        I am surprised that nearly one month after my initial post no one from Cypress bothered to answer this simple question or post a link to a document where this will be answered. A quick chat with a chip designer will have been enough to obtain this information but it might be the case that Cypress is such a big company that marketing and/or application engineers don't even know who are the chip designers.   

[saiprashanthc_]

        FEC is not implemented in CyFi. It has the CRC check . When the bytes are transmitted from transmitter to receiver . The receiver checks for the CRC and ensures the reliable communication.   
   
Regards,   
Sai Prashanth   
Applications Engineer   

[Anonymous]

        Thanks Sai Prashanth for the useful reply. That confirms my suspicion stated above. Anyway the upper protocol layers will be able to request a retransmission based on the CRC check.   
   
One can view a FEC scheme as a way to improve the receiver sensitivity by several dBs, but it costs gate area and power consumption. Usually FEC is cheaper than achieving it (better Rx sens.) by other means, probably not in this case.   
   
Regards