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1. Check the maximum column clock vs. operating power of the DAC. The maximum column clock is highest when you operate the DAC at High Power and lowest when operated at low power.
2. Check the Analog Power setting in global resources. The power should be equal to or greater than the power at which you run the DAC. For example, if you start the DAC at medium power, the Analog Power parameter should be "SC On / Ref Med" or "SC On / Ref High"
Tnx for the suggestions. I managed to lower the offset to 40mV by lowering the DAC power setting to medium and lowering the buf setting to low.
Now i founded that i have another problem. My DAC pin has at startup a spike to 4V. Any idea how i can fix this?
This may be because of the initial value on the DAC when you start it. Try the below workaround.
1. In the device editor, do not connect the analog output pin to the analog buffer. Just connect the output of the DAC to the analog bus and leave the buffer off.
2. In main.c first start the DAC and write 0x00. This will set the output of the DAC to AGND.
3. Now switch on the Analog buffer using the ABF_CR register.
Well i limited the spike so that the spike is there for 7.5uS at the beginning. Is there any way how i could reduce the offset more? so it will be 20mV max?