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The Alternate Active mode is used to disable peripherals which are not required. Since the combination is very huge, we don't have an API to do it. The API CyWait will change the mode to Alternate Active. But before that you should decide which peripherals are required. That is done using the STANDBY registers. These registers start from location 0x43B0 and you can find then cydevice.h as CYDEV_PM_STBY_CFG0 etc. We have to use these registers to control which peripherals should be enabled. And then Cy_Wait should be called.
So, if a peripheral is enabled using the STANDBY registers, will the BUS_CLK be active after CyWait is called?
Yes it will. All MHz frequency clocks are active in Alt. Active mode, unless otherwise specified by the user.