4 Replies Latest reply on Apr 9, 2010 3:28 PM by alexander.vasiljev

    ep8 and fifo out

    alexander.vasiljev
              Hi guys.   
         
      We are developing a usb project with Cy7c68013A-100. We have heavy input traffic and light output traffic. So we dicided to use ep2 as input endpoint and ep8 as output.   
         
      But we can't get output data from the fifo pins (FD0 - FD15). FIFOADDR is set to "11". FLAG is signaling like data is going through.   
         
      Then we turn things upside down and set ep2 as output endpoint and ep8 as input. And the data appears on the fifo pins, so everything works well.   
         
      Does it mean that we can't use ep8 as output endpoint, or we missed something significant?   
        • 1. Re: ep8 and fifo out
          anand.srinivasan.asokan
                  In page 32 of the trm the 12 possible endpoint configurations is displayed. Are you following this?   
          • 2. Re: ep8 and fifo out
            alexander.vasiljev
                    Yes. We have used the 11th conifguration (ep2 1024 x 3, ep8 512 x 2), when ep8 was output. And the first configuration (ep2 512 x 2, ep8 512 x 2), when ep2 was output.   
            • 3. Re: ep8 and fifo out
              anand.srinivasan.asokan
                      I'll see if i can test what you are describing... i remember ep8 working fine...   
              • 4. Re: ep8 and fifo out
                alexander.vasiljev
                        Here is TD_Init function:   
                   
                CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); SYNCDELAY; // set the CPU clock to 48MHz   
                   
                SYNCDELAY;   
                   
                IFCONFIG = 0x03; SYNCDELAY;   
                // 0 0 0 0 0 0 1 1   
                // | | | | | | | |   
                // | | | | | | slave fifo interface   
                // | | | | | port e no gstate   
                // | | | | slave fifo's operate synchrously   
                // | | | IFCLK is not inverted   
                // | | IFCLK in tri-state   
                // | internal clockis 48Mhz (not used)   
                // external clock source on IFCLK   
                   
                REVCTL = 0x03; SYNCDELAY;SYNCDELAY;//Cypress highly recommends setting both bits to '1'.s   
                   
                EP2CFG = 0xEB; SYNCDELAY;   
                // 1 1 1 0 1 0 1 1   
                // | | | | | | | |   
                // | | | | | | triple   
                // | | | | | reserved   
                // | | | | 1024   
                // | | bulk   
                // | in   
                // valid   
                   
                EP8CFG = 0xA2; SYNCDELAY;   
                // 1 0 1 0 0 0 1 0   
                // | | | | | | | |   
                // | | | | | | double   
                // | | | | | reserved   
                // | | | | 512   
                // | | bulk   
                // | out   
                // valid   
                   
                EP4CFG = 0; SYNCDELAY;   
                EP6CFG = 0; SYNCDELAY;   
                   
                EP1OUTCFG = bmBIT5; SYNCDELAY; //Invalid, bulk   
                EP1INCFG = bmBIT5; SYNCDELAY; //Invalid, bulk   
                   
                //Nak all and reset the endpoints   
                FIFORESET = 0x80; SYNCDELAY;   
                FIFORESET = 0x02; SYNCDELAY;   
                FIFORESET = 0x08; SYNCDELAY;   
                FIFORESET = 0x00; SYNCDELAY; //Restore normal operation   
                   
                OUTPKTEND = 0x88;SYNCDELAY;   
                OUTPKTEND = 0x88;SYNCDELAY;   
                   
                EP2FIFOCFG = 0x0D; SYNCDELAY;   
                // 0 0 0 0 1 1 0 1   
                // | | | | | |   
                // | | | | | 16bit   
                // | | | | z-len send allowed   
                // | | | autoIN (applies only to IN endpoints)   
                // | | no autoOUT (applies only to OUT endpoints)   
                // | OEP (applies only to OUT endpoints)   
                // INFM (applies only to IN endpoints)   
                   
                EP8FIFOCFG = 0x11; SYNCDELAY;   
                // 0 0 0 1 0 0 0 1   
                // | | | | | |   
                // | | | | | 16bit   
                // | | | | z-len send not allowed   
                // | | | no autoIN (applies only to IN endpoints)   
                // | | autoOUT (applies only to OUT endpoints)   
                // | OEP (applies only to OUT endpoints)   
                // INFM (applies only to IN endpoints)   
                   
                EP4FIFOCFG = 0; SYNCDELAY;   
                EP6FIFOCFG = 0; SYNCDELAY;   
                   
                EP2AUTOINLENH = 0x04; SYNCDELAY; //1024   
                EP2AUTOINLENL = 0x00; SYNCDELAY;   
                   
                // since the defaults are double buffered we must write dummy byte counts twice   
                SYNCDELAY;   
                EP8BCL = 0x80; // arm EP8OUT by writing byte count w/skip.   
                SYNCDELAY;   
                EP8BCL = 0x80;   
                   
                SYNCDELAY;   
                EP0BCH = 0;   
                SYNCDELAY;   
                EP0BCL = 0;   
                SYNCDELAY;   
                   
                FIFOPINPOLAR = 0x00; SYNCDELAY;   
                // 0 0 0 0 0 0 0 0   
                // | | | | | | | |   
                // | | | | | | | full flag polarity (active low)   
                // | | | | | | empty flag polarity (active low)   
                // | | | | | slwr polarity (active low)   
                // | | | | slrd polarity (active low)   
                // | | | sloe polarity (active low)   
                // | | pktend polarity (active low)   
                // not used   
                   
                PINFLAGSAB = 0xBC;SYNCDELAY;   
                // 1 0 1 1 1 1 0 0   
                // | | | | | | | |   
                // | | | | flag A indicates ep2 full   
                // flag B indicates ep8 empty   
                   
                PORTACFG = 0;SYNCDELAY;   
                // 0 0 0 0 0 0 0 0   
                // | | | | | | | |   
                // | | | | | | | PA0 - not int0   
                // | | | | | | PA1 - not int1   
                // | | not used   
                // | SLCS   
                // PA7 - not FlagD