3 Replies Latest reply on Apr 9, 2010 3:34 PM by andrew.sobotka

    how to config slave fifo interface in CY7C68013A-128AXC

    fenglei.yuan
              hi guys,   
         
      recently, I'm developing a usb project, in which Cy7c68013A-128AXC is used to communicate with FPGA through slave fifo interface,   
      in the 68013, EP2 is configured as 512 bytes double buffered mannual out fifo, EP6 is configured as 512 byte double buffered auto-in fifo, IFCLK is coming from external.   
         
      after painful debugging, I saw very strange behavior in the slave fifo interface:   
         
      when FPGA read data from 68013 through slave fifo interface, we must set the SLOE bit of FIFOPINPOLAR register to be '1', after that, FPGA can correctly read data from slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.   
      otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '0', then we can never read data out from slave fifo even we drive SLOE pin to '0', the data bus on slave fifo looks like in HighZ state.   
         
      when FPGA write data into 68013, the condition is contrary to read data from 68013. we must set the SLOE bit of FIFOPINPOLAR register to be '0', after that, FPGA can correctly write data into 68013 through slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.   
      otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '1', then we can never write data into 68013 through slave fifo interface, even we drive SLOE pin to '0'.   
         
      and I'm sure that the SLOE pin connection is ok, it's not floating.   
         
      following is TD_init() in 68013 firmware, is there any wrong configuration??   
         
      void TD_Init(void) // Called once at startup   
      {   
      // set the CPU clock to 48MHz   
      CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;   
         
      REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1   
      SYNCDELAY; //   
      FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions   
      SYNCDELAY; //   
      FIFORESET = 0x02; // reset, FIFO 2   
      SYNCDELAY;   
      FIFORESET = 0x06; // reset, FIFO 6   
      SYNCDELAY; // //   
      FIFORESET = 0x00; // deactivate NAK-ALL   
      SYNCDELAY;   
         
      // set the slave FIFO interface to 48MHz, use external clock   
      IFCONFIG = 0x43;   
      SYNCDELAY;   
         
      EP2FIFOCFG = 0x01; // mannual out   
      SYNCDELAY;   
      EP2CFG = 0xA2;   
      SYNCDELAY;   
      EP6FIFOCFG = 0x09; // autoin   
      SYNCDELAY;   
      EP6CFG = 0xE2;   
      SYNCDELAY;   
         
      // !!!!!! when external fifo master read data from slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 1, FIFOPINPOLAR = 0x10   
      // !!!!!! when external fifo master write data into slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 0, FIFOPINPOLAR = 0x00   
      FIFOPINPOLAR = 0x00;   
      SYNCDELAY;   
         
      EP6AUTOINLENH = 0x02; // you can define these as you wish,   
      SYNCDELAY; // to have the FX2 automatically limit IN's   
      EP6AUTOINLENL = 0x00;   
      SYNCDELAY;   
         
         
      SYNCDELAY;   
      EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.   
      SYNCDELAY;   
      EP2BCL = 0x80;   
      SYNCDELAY;   
         
      // enable dual autopointer feature   
      AUTOPTRSETUP |= 0x01;   
         
      Rwuen = TRUE; // Enable remote-wakeup   
      }   
         
         
        • 1. Re: how to config slave fifo interface in CY7C68013A-128AXC
          andrew.sobotka
                  I would suggest triple-checking your SLOE connection. If the FX2's FIFO data bus drivers do not appear to respond to your FPGA toggling the SLOE signal, then the SLOE pin must be stuck at the FX2. Given that you need to set FIFOPINPOLAR<4> to 1 to get the FX2 to drive the FIFO data bus, this means the SLOE pin is stuck at 1.   
             
          Can you attach a scope to the SLOE pin at the FX2, not the FPGA? You need to verify that the signal is actually toggling at the FX2's pin. A short somewhere in the circuit could be preventing the FPGA from successfully driving the FX2's SLOE pin low.   
             
          Are you sure you have the correct pinout for your FX2? You're using the 128 pin part, and the pinout can be different from the 100 and 56 pin parts.   
             
          Are you sure you're using the correct pinout for your FPGA? Does your constraint file connect the internal SLOE signal to the correct output pin? Are you sure the FPGA's SLOE output pin is actually connected to the FX2's SLOE input?   
          • 2. Re: how to config slave fifo interface in CY7C68013A-128AXC
            fenglei.yuan
                    Hi andrew,   
               
            thanks for your response. after exactly making sure that the connection is ok, and directly probe the SLOE pin in the 68013 chip, it also looks fine, it has been correctly driven by FPGA and the SLOE pin in 68013 side could correctly toggle.   
               
            I have no choice but replacing the 68013 chip, thank god, it works.   
               
            definitely, there is something wrong in the SLOE circuits inside the 68013 chip.   
               
            after that I encountered another issue when I using AUTO OUT transfer.   
            before starting auto-out transfer, we need to skip and arm the buffer in Toll_init()   
            my problem is,   
            1.when I set REVCTL=0x03, PC can not send bulk out data to 68013, EZ-USB control panel will always pend this request.   
            2.after setting REVCTL=0x01, and writting OUTPKTEND=0x8x in Toll_init to SKIP and arm the buffer, EZ-USB control panel will always pend bulk out request from PC   
            3.after setting REVCTL=0x01, and writting EPxCBL=0x80 in Toll_init to SKIP and arm the buffer, EZ-USB control panel can send bulk out data to 68013.   
            then there is something interesting: EZ-USB control panel send out only one packet, but 68013 send more than one packet to slave fifo interface, sometimes sends out 2 packet, sometimes 3 or 4 packets   
               
            do you have any clue or suggestion?   
               
            BR,   
            Fenglei   
            • 3. Re: how to config slave fifo interface in CY7C68013A-128AXC
              andrew.sobotka
                      Hi Fenglei,   
                 
              For reasons I cannot remember, I do not use REVCTL=0x03 (DYN_OUT=1 and ENH_PKT=1). I only use ENH_PKT=1   
                 
              The Technical Reference Manual has information under the REVCTL register that states when DYN_OUT=0, a 0->1 transition of the AUTOOUT bit will cause the endpoint to become armed (potentially losing any data during the manual-out->auto-out transition). That is, you should NOT need to arm the endpoint by writing to OUTPKTEND or writing to EPxBCL. Unfortunately, if there was any data waiting for you to read from the Endpoint's buffer during the 0->1 transition, it will be gone because the buffer will be available for new data.   
                 
              That is why they made DYN_OUT=1. In this case, you must "prime the pump" by arming the endpoint with OUTPKTEND or EPxBCL.   
                 
              Here is the general approach that I take when initializing the FX2. First, set CPUCS for the clock speed, CKCON for the stretch value, IFCONFIG for the FIFO interface, and then REVCTL. In this case, I set REVCTL |= bmSKIPCOMMIT; This is the same as REVCTL=0x01   
                 
              Next, I configure the USB Domain side of the FIFO (e.g. the side that communicates with the USB host controller). This is the EPxCFG registers. FYI, the USB Domain's status registers are EP24FIFOFLGS and EP68FIFOFLGS. The status bits are copied together into EP2468STAT, which is conveniently in SFR space.   
                 
              Then, I set FIFORESET (remember to set 0x80 to NAK all, then 0x0X where X is the endpoint to reset, and then 0x00 to stop NAK all). I think there's a reason I do FIFORESET between configuring the USB and Peripheral domains but it eludes me currently.   
                 
              Next, I configure the Peripheral Domain side of the FIFO (e.g. the side that communicates with external logic, in your case the FPGA). This is the EPxFIFOCFG registers. The corresponding status registers for this domain are EPxFIFOFLGS.   
                 
              Of very important note is that the AUTO-OUT (and maybe the AUTO-IN?) bits need to experience a 0->1 transition here. Now, when the FX2 comes out of Power On Reset, these bits are 0, and you normally set them to 1. However, if you do a warm reset (such as using the CPUCS register's Reset bit) the bits will stay 1 and give you a headache.   
                 
              Finally, if there are any endpoints left that require arming (like EP1, which doesn't have AUTO- bits), I arm them last.   
                 
              May I suggest comparing the status of the two domains? Some problems can be diagnosed by observing desynchronization of the endpoint's status between the two domains. One example would be the Peripheral domain indicating that it is full while the USB domain indicates that it is empty; the FX2 will tell the USB host controller that it has no data available, while it tells the external logic that it has no buffers available.