0 Replies Latest reply on Apr 9, 2010 6:16 PM by userc_44996

    Programming FX2 FIFO Full threshold

              I have set up EP4 on an FX2 as an IN endpoint, operating in    Full speed mode (USB 1.1). The packet size is set to 64 bytes, and EP4 is configured for double buffering ( which apparently is the only available option) and AUTOIN=1.   
      A couple of questions --   
      1. On programming EP4FIFOPFH/PFL with DECIS = 1, PKTSTAT = 0 and IN: PKTS[1:0] = 0, PFC[5:0] = 32, after the external master writes the 32nd byte, the full flag gets asserted ( after a delay tXFLG). The external master continues to write an arbitrary number of bytes (say, 12), before deasserting SLWR. Would this lead to a deadlock situation, as the FIFO is "full", and it can never empty as there isn't a complete packet yet (only 44 bytes in the FIFO, which is lesser than the 64 bytes required to complete a packet)?   
      2. Is setting PKTSTAT = 1 the same as {PKTSTAT=0, IN: PKTS[1:0] = 0}?