Using 68013A 8bit synchronous slave FIFO interface.
EP2 as Hi-speed Bulk IN. FlagA - programmable FULL.
I use FPGA with ChipScope to test FlagA status.
Test: write enable = inactive, continuous clock at IFCLK. I see FlagA toggling. Seems that period proportional to clock period (tested with 33...6 MHz IFCLK). When reading BULK endpoint from CyConsole STALL reported. Reconnecting not help. Asynchronous FIFO interface work (at least no STALLs).
Problem was solved with help of Cypress Support.
It was: no input IFCLK when I switch to external clock (IFCONFIG.7 = 0).