2 Replies Latest reply on Jun 14, 2010 12:19 PM by JeVE_287651

    Bug in verilog '-' ?




      I think that (maybe) there is a bug in the subtraction verilog implementation of 2 variables :     


          The following module  is a saw generator with an incremented offset. If you change the "+ offset" in "- offset", the result is completely false (uncomment the next line). If you convert “-x“ in  “~x + 1” the result is correct.        





      To visualize the result, simply connect the DA to the outp, and clock the module with a 100kHz, for example…







      `include "cypress.v"//`#end` -- edit above this line, do not edit this line// Generated on 05/26/2010 at 12:40


      // Component: bugtest


      module bugtest (








      output [7:0] outp;


      input   clk;



      //`#start body` -- edit after this line, do not edit this line


      reg [7:0] outp;


      reg [15:0] offset;


      reg [4:0] saw;


      always @(posedge clk)




      // saw generator


      saw <= saw + 1;


      // offset


      offset <= offset + 1;


      // add is OK


      outp <= {3'b0, saw} + offset[15:8];


      // BUG if sub


      // outp <= {3'b0, saw} - offset[15:8];


      // corrected sub is OK


      // outp <= {3'b0, saw} + ~offset[15:8] + 1;





      //`#end` -- edit above this line, do not edit this line



        • 1. Re: Bug in verilog '-' ?

          Your analysis is very much correct.  There was an error in the implementation of subtraction when mapped to the PSoC 3 PLD architecture.  We've found the specific problem and are in the process of completing the fix.  This will be included in the next version of PSoC Creator which is Beta 5.  That tool version will come out during Q3.


          It should be noted that this problem only applies for a full subtraction.  It does not apply when subtracting a constant (ie. decrementing) which is handled with a different implementation.


          Thank you for bringing this to our attention.


          Brad Budlong
          PSoC Sensei

          • 2. Re: Bug in verilog '-' ?

             "It should be noted that this problem only applies for a full subtraction"


            hummm... not only the subtraction.


            for exemple if you do


            c = {b,1'b0} - a; // the result is false


            if you do


            c = {b,1'b0} + ~a + 1; // the result is good but


            c = {b,1'b0} + 1 + ~a; // the result false 


            idem with


            c = {b,1'b1} + ~a; // the result is false...


            I think that sometime (?) the fitter change the addition with the (bugged) subtraction...




            Jean-Louis VERN