3 Replies Latest reply on Sep 15, 2010 4:00 PM by alex.bogias

    Read/Write from 64k*16 SRAM  - CY7C1021DV33

    alex.bogias

      Dear all,

         

          

                

         

      Thanks for taking the time to read my post.

         

          

                

         

      I am currently researching WLAN data acquisition sensors and I have designed and manufactured a PCB using Cypress Asynchronous SRAM CY7C1021DV33, for data storage.

         

          

                

         

      I am using a microcontroller running at 40MHz (25ns cycle) to write/read from the CY7C1021DV33.

         

          

                

         

      Everything works smoothly when I write and then read one 16-bit variable to/from SRAM memory, but when I try and write/read two consecutive 16-bit variables to/from SRAM memory, I seem to read back un-expected data.

         

          

                

         

      I have never used external parallel memory, only serial, so I am a bit perplexed as to the steps needed to perform consecutive read/writes from memory.

         

          

                

         

      I have added my code (in C) below, with a few comments explaining, what I am trying to do.

         

          

                

         

      I would be grateful if someone could point, as to what I am possibly doing wrong.

         

          

                

         

          

            []    

         

      /************************************************************************************
      * Write SRAM routine
      ************************************************************************************/
      void writeSRAM(void)
      {
      sram_change_port_function = 0b0000000000000000;        //PORTD is an output

      SRAM_write_addr = SRAM_write_addr+1;        // Increment address

      //Set Control pins
      sram_control_port=0b00100000;            // Write all bits - OE, WE cleared
                                             
      //Set Address
      sram_port_address=SRAM_write_addr;

      //Write Current Data
      sram_data_port_write=g_adc_data_I1;

      //Set control pins
      sram_control_port=0b00100110;            //OE SET, WE SET, Outputs disabled

      //Store Voltage in SRAM

      //Increment address
      SRAM_write_addr=SRAM_write_addr+1;

      //Set Control pins
      sram_control_port=0b00100000;            //Write all bits - OE, WE Cleared
                                            
      //Set Address
      sram_port_address=SRAM_write_addr;

      //Write VoltageData
      sram_data_port_write=g_adc_data_V1;

      //Set control pins
      sram_control_port=0b00100110;            //OE SET, WE SET, Outputs disabled

      }//writeSRAM

         

       

         

       

         

      /************************************************************************************
      * Read SRAM routine
      ************************************************************************************/
      void readSRAM(void)
      {
      sram_change_port_function = 0b1111111111111111;    //PORTD is an input

      SRAM_read_addr = SRAM_read_addr+1;        // Increment address

      //Set Control pins
      sram_control_port=0b00100100;            //Read all bits - WE Set, OE cleared
                                            
      //Set Address
      sram_port_address=SRAM_read_addr;

      //Read Current Data
      SRAM_data_I=sram_data_port_read;

      //Set control pins
      sram_control_port=0b00100110;            //OE SET, WE SET, Outputs disabled

      //Read Voltage from SRAM

      //Increment address
      SRAM_read_addr = SRAM_read_addr+1;       

      //Set Control pins
      sram_control_port=0b00100100;            //Read all bits - WE Set, OE cleared
                                           
      //Set Address
      sram_port_address=SRAM_read_addr;

      //Read Voltage Data
      SRAM_data_V=sram_data_port_read;

      //Set control pins
      sram_control_port=0b00100110;            //OE SET, WE SET, Outputs disabled

      }//readSRAM

         

       

         

       

         

      [/]

         

          

                

         

      Thanks

         

      Alex

        • 1. Re: Read/Write from 64k*16 SRAM  - CY7C1021DV33
          alex.bogias

          Hi all,

             

              

                     

             

          I will try and take a step back and try and explain what I think I am telling the SRAM memory to do.    

               
              

             

          I think my code can look daunting and/or badly written, so here is what I think I am doing.

             

              

                     

             

          Write routine     

           

              

               
              

             

          1. Set microcontroller I/O port as an output.    

               
              

             

          2. Increment ‘write’ address variable.    

               
              

             

          3. CE, OE, WE, BHE, BLE cleared. Ready to write.    

               
              

             

          4. Write address to SRAM.    

               
              

             

          5. Write data to SRAM.    

               
              

             

          6. OE, WE SET. CE, BHE, BLE cleared. Outputs disabled

             

              

               
              

             

          Repeat steps 2-6 to write second 16-bit variable to memory.

             

              

                     

             

              

                     

             

          Read routine     

           

              

               
              

             

          1. Set microcontroller I/O port as an input.    

               
              

             

          2. Increment ‘read’ address variable.    

               
              

             

          3. CE, OE, BHE, BLE cleared. WE set. Ready to read.    

               
              

             

          4. Write address to SRAM.    

               
              

             

          5. Read data from SRAM.    

               
              

             

          6. OE, WE SET. CE, BHE, BLE cleared. Outputs disabled

             

              

               
              

             

          Repeat steps 2-6 to read second 16-bit variable from memory.

             

              

                     

              

               
              

             

          As I said in my previous post, I have never used parallel Async SRAM before, so the timing relationships between control pins, address pins and I/O pins are a bit perplexing to me.    

           

              

               
              

             

          I am not sure whether the 25ns cycle time of the microcontroller might be too slow for the memory and unexpected data are written/read because of this inherent delay.    

               
              

             

          As far as I know, reading/writing to/from I/O pins will take one cycle (25ns) and writing to the Control pins and Address pins will also take one cycle each. Are these timings ‘good enough’ for the SRAM chip?

             

              

                     

             

          Any advice would be more than welcome.

             

              

               
              

             

          Thanks and regards

             

          Alex

          • 2. Re: Read/Write from 64k*16 SRAM  - CY7C1021DV33
            alex.bogias

            After more debugging, I think I have solved the problem I was having.

               

                

                      

               

            It seems that ‘writing address to SRAM’ has to take place BEFORE the Control pins are Set/Cleared. I was suspicious that this might be the case, as the ‘Switching Waveforms’ section of the CY7C1021DV33 datasheet (Read Cycle No.2) seems to show this pretty clearly. CE Low to Data Valid (tACE) is meant to take a maximum of 10ns AFTER the ‘Write Address’ has started.

               

                

                      

               

            HOWEVER what is not clear to me is why I also had to a delay, which in my case is 25ns (the minimum possible) in the read routine AFTER the ‘Read data from SRAM’ (point 5) has taken place.

               

                

                      

               

            I was under the impression that enough time (25ns) has lapsed since the ‘Read Command’ has been sent (point 4), for valid data to appear on the ASYNC SRAM I/O pins.

               

                 

                        

               

            Below you will find the ‘corrected’ explanation of what my read/write routines looks like.     

             

               

                

                      

               

            Write routine
                
                

               

            1. Set microcontroller I/O port as an output.

               

            2. Increment ‘write’ address variable.

               

            3. Write address to SRAM.

               

            4. CE, OE, WE, BHE, BLE cleared. Ready to write.

               

            5. Write data to SRAM.

               

            6. OE, WE SET. CE, BHE, BLE cleared. Outputs disabled

               

            7. Repeat steps 2-6 to write second 16-bit variable to memory.

               

             

               

             

               

            Read routine
                
                

               

            1. Set microcontroller I/O port as an input.

               

            2. Increment ‘read’ address variable.

               

            3. Write address to SRAM.

               

            4. CE, OE, BHE, BLE cleared. WE set. Ready to read.

               

            5. Read data from SRAM.

               

            6. One cycle Delay (25ns).

               

            7. OE, WE SET. CE, BHE, BLE cleared. Outputs disabled

               

            8. Repeat steps 2-7 to read second 16-bit variable from memory.

               

                

                      

               

            I would be grateful if anyone could have a look at my posts and maybe suggest some possible reasons why this might be happening.

               

                

                      

               

            I would also be grateful if someone could point to some good Ap Notes, Books and/or websites that detail ASYNC SRAM chips and the issues surrounding them.

               

                

                      

               

            Thanks and regards

                Alex
            • 3. Re: Read/Write from 64k*16 SRAM  - CY7C1021DV33
              alex.bogias

                             After a summer pause and some more testing, I realized the code as described above does not work.

                 

              It seems the sequence of steps for the Reading routine was wrong.

                 

              The below does seem to work:

                 

               

                 

              Write routine

                 

              1. Set microcontroller I/O port as an output.

                 

              2. Increment ‘write’ address variable.

                 

              3. Write address to SRAM.

                 

              4. CE, OE, WE, BHE and BLE cleared. Ready to write.

                 

              5., CE, WE, BHE and BLE Set. OE cleared. Outputs disabled

                 

              6. Write data to SRAM.

                 

              7. Repeat steps 2-6 to write second 16-bit variable to memory.

                 

              Read routine

                 

              1. Set microcontroller I/O port as an input.

                 

              2. Increment ‘read’ address variable.

                 

              3. Write address to SRAM.

                 

              4. CE, OE, BHE, BLE cleared. WE set. Ready to read.

                 

              5., CE, WE, BHE and BLE Set. OE cleared. Outputs disabled

                 

              6. Read data from SRAM.

                 

              7. Repeat steps 2-7 to read second 16-bit variable from memory.

                 

               

                 

              Through testing of the Write routine, I ‘think’ it does not matter if Step 5 or 6 come first. But it is crucial that step 5 comes before 6 for the Read routine. I am not sure why changing the sequence of steps 5 and 6 would have this drastic effect.

                 

              I hate re-inventing the wheel, so could someone please provide me with a plausible answer.

                 

              I also, once every couple of seconds, get what seems to be a bad memory read/write. I am not 100% sure if this is because of the sequence of my read/write routines, or because I have added or missed some part of code. There are simply infinite variation I could try.

                 

              I would be grateful if a member of this forum provides some help, with the right write/read steps.

                 

              Should I contact Technical support with my problem?

                 

              Someone must have done something similar before….