Through the Cypress MyCase assistance, I was supplied with a .pdf detailing the device topology and showing the translation of External Address lines A0 to A17 with Internal Row and Column Address lines. Address changes that just affect the lsbit of the Internal Column Address and/or just the lsbit of the Row Address result in addressing physically adjacent memory. For this device, addresses that differ by just Address Lines 0 and 9 are physically adjacent memory locations. As in my case, others may need to consider the external bus mapping to their processor interface, as, particularly using this 16-bit wide part, it is possible that the processor has an AD(0) line that may not be mapped to this device.
Application note AN15979 indicates that MBU is "virtually impossible" due to the spacing of adjacent cells, and that no MBU had been recorded "in all SER testing" at the point that the application note was written.
Non-the-less, as a general guide, it is always good to know how physically adjacent cells are addressed. In absence of this info, using three copies of your critical data, the base address for each of which differ by three different powers of 2 from the other two, should help keep your data safe from MBU.