I have a problem with conversion rate in ADC_DelSig.
My config is:
* High Power
* Continuous Mode
* Resolution: 12b
* Conversion Rate: 50000 SPS
* Clock frequency: 1600 KHz
* Input Range: Input+/- Vref/4
* Buffer Gain: 8
The datasheet states: (See screenshot attached).
I'm interested in the Continuous mode column.
The program put's you an error message if you exceeds the 600KHz datasheet of clock frequency, but
the datasheets don't sais that.
I tried to put a external source clk with higher freq. The error message still apearing.
What I'm doing wrong?
How I could reach higher samples rates arround 50000 or 100000 SPS?
The problem is not the ADC.
The problem was found to be the Ins Amp Gain*Bandwidth product: G*B=3MHz.
Is not a limitaton of the DAC itself, insted of is the speed limitation and the capability of my Ins Amp to
provided me a stable data with no transitions errors.
So the solution is to g down the Ins Amp Gain.