Anonymous
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Mar 01, 2011
09:15 PM
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Mar 01, 2011
09:15 PM
I use the 68013A, GPIF mode, the FIFO write, found that each write of n data , the length of WR_FIFO signal is longer than n datas' length, the result is that n+1 datas wrote into the FIFO. why ?
1 Reply
Anonymous
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Mar 02, 2011
03:20 AM
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Mar 02, 2011
03:20 AM
Hi,
Please check whether you have a state after the WR_FIFO signal assertion which deasserts this signal and jump to the idele state after that stste.
Also if you can attach the firmware and gpif waveform I will be able to help you more on this.
-Shubham