I try source a complete OUT packet to the slave fifo interface.
Pipe 4 is in manual mode and all packets from the host need to be commited to send out to the peripheral device (FPGA).
This works fine, but i need to commnicate with the FPGA without host interaction.
I follow the example code from the TRM.
I see the new sourced packet comming out to the FPGA only when a packet is received on pipe4 from the host.
What do I missing here?
in TD_POLL:
if( EP24FIFOFLGS & 0x20 ) {
SYNCDELAY; //
FIFORESET = 0x80; // nak all OUT pkts. from host
SYNCDELAY; //
FIFORESET = 0x84; // advance all EP4 buffers to cpu domain
SYNCDELAY; //
EP4FIFOBUF[0] = 0x0; // create newly sourced pkt. data
SYNCDELAY; //
EP4BCH = 0x00;
SYNCDELAY; //
EP4BCL = 0x40; // commit newly sourced pkt. to interface fifo
// beware of "left over" uncommitted buffers
SYNCDELAY; //
OUTPKTEND = 0x84; // skip uncommitted pkt. (second pkt.)
// note: core does not allow pkts. to get out of sequence
SYNCDELAY; //
FIFORESET = 0x00; // release "nak all"
}
