A nvSRAM memory cell integrates a fast access SRAM cell and a non volatile NV cell in a monolithic die. This cell structure offers the benefit of high performance SRAM access and non volatility of EEPROM/FLASH. In a typical system configuration where the system controller uses external memories for storing its firmware program and data, a Flash memory is used to store the program code and a SRAM is used to store runtime data and variables. During system boot up, the firmware code is first dumped into SRAM from the flash and then executes from SRAM.
Since the nvSRAM combines SRAM and NV cells, it can potentially replace the combination of SRAM and FLASH with a single memory. After a power cycle, the data stored in NV cells of nvSRAM is available to SRAM after 20 ms (Power up Recall duration) which can be used by the controller for its boot up process. Once boot up process completes, the same SRAM space can be used as data memory for storing run time variables, parameters and scratch pad data. In this used model, the AutoStore feature of nvSRAM must be disabled so that SRAM data is never written back to its NV cell on its own by performing an AutoStore cycle. This will ensure that NV portion always stores the F/W program code. Disabling AutoStore features makes NV memory in nvSRAM as read only memory (ROM). To program the nvSRAM again with a new F/W code and store in its NV cell, on demand Software Store command can be issued which will Store a new code into its NV cell.
The only drawback with this approach is that data is not available in the SRAM for the first 20 ms during power up RECALL duration. It means controller boot up will start only after 20 ms. After 20 ms entire program memory is available in SRAM, whereas in SRAM+Flash combination, controller initially copies code from the program memory (Flash) to data memory (SRAM) on byte by byte basis.