0 Replies Latest reply on Mar 25, 2011 5:56 AM by userc_44715

    AN66806 - Design Example 1: 16 bit interface to external FIFO Auto Mode

       I am using appnote AN66806, design example 1: 16 bit interface to external FIFO Auto Mode


      I have CY3684 cypress dev kit for CY7C68013A (FX2) processor. I have 'lashed' an XiLinx to the FX2 to mimmic a FIFO.


      Everything codewise is the same as the appnote


      However I am getting too many clock pulses per 512 byte (256 - 16 bit word) transfer.


      I am trying to read data out of the FIFO into the FX2 and then across USB to a PC using Cyconsole. I have sent the B3 vendor command to enable IN transfers and I get data.


      The FPGA fills the FIFO which is 4k Words deep with a rolling count. When I request a 512 byte block, I get values and the fifo starts to empty but I am missing two words for every transfer. The first packet ends with say FF 00 00 01 (0x00FF, 0x0100) and the next packet starts 03 01 04 01 (0x0103, 0x0104)


      What is the silly mistake I am making?


      Thanks for your suggestions in advance