4 Replies Latest reply on May 6, 2011 8:08 PM by userc_44640

    Question about JTAG/SWD pins needed for new design

      G'day all,




      I'm about to finalise the design of my rover using the CYC5588AXI-060. It's replacing a Zilog eZ80F91 module, which only required 2 debug/programming pins, TCK and TDI (and ground, obviously!).




      However, I'm unclear about exactly which pins are required for the SWD mode debug/programming interface. I'd appreciate it if someone could confirm exactly which pins need to be connected to the header for non-JTAG programming. I'd also like to understand if I need to make any changes to the programming routine if only the SWD pins are used. The family and device datasheets mention switching to SWD from the JTAG connection, but not details of which of the common pins need to be connected first. Any help would be appreciated!







        • 1. Re: Question about JTAG/SWD pins needed for new design
          • PSoC5/PSoC5 can be programmed and debugged using two interfaces namely SWD and JTAG. For SWD to work typically two pins, SWDIO(data line) and SWDCK(Clock line) are necessary. For JTAG debugging there are two modes namely 4 wire mode and 5 wire mode.  For the 4 wire mode 4 pins TMS,TCK,TDO,TDI are used. For 5 wire mode an additional NTRST is required. 
          • Same pin is used for SWDIO and TMS. Same pin is used for SWDCK and TCK.
          • PSoC3 chip needs to go through a acquire sequence for programming and debugging. The existing MiniProg3 uses SWD interface to acquire the device. Once the device is acquired using SWD, it can be programmed and debugged uisng SWD or JTAG by chooisng the approriate mode.
          • In your case All you need is SWDIO,SWDCK, XRES and power pins. XRES pin is required to acquire the device by applying reset.
          • 2. Re: Question about JTAG/SWD pins needed for new design

            I would recommend that you go through the Programming, Debug interfaces section of the application note AN61290- Hardware Starting Guide with PSoC® Creator available at www.cypress.com/

            • 3. Re: Question about JTAG/SWD pins needed for new design

                Thanks guys, I've been through all the manuals and datasheets, but I wanted to confirm, as there's no actual schematic apart from the devkit (001) - which includes all the JTAG pins. I know why they need to be connected on the devkit, but that doesn't help me specifically...


              Reading the Miniprog3 guide, it seems that TMS and TCK are enough when the programming mode is switched to SWD on the Miniprog, which kinda confirms what the datasheets mention.




              But I'm not sure about SWV. That isn't mentioned as part of either SWD or JTAG debugging, apart from the fact that it can be used for printf-style debugging. I'm unclear about whether or not I need to connect SWV as part of the "2 wire debug". In other words, is some kind of debug/viewing functionality included if I use only the SWD debugging pins, or must I connect SWV if I want that as an additional function?


              I've already routed and connected the TMS and TCK pins to the debug header, as per the datasheet. I'll also connect  SWV, I have enough board space.

              • 4. Re: Question about JTAG/SWD pins needed for new design

                 Ah, OK, now I've read AN61290, and of course it is much clearer. Thanks so much for that reference, it's really handy. Maybe Cypress could include this in the "related documents" for the PSoC 3/5 product pages? That would help other designers too.


                For anyone who's interested, here are the details for "2 pin" debugging with SWD.


                First and foremost, SWD debugging is at least a 4-pin debugging option, NOT 2 pin. This is not at all clear from the CY8C55 Family Datasheet, the PSoC 3/5 Architecture TRM, nor the supplied documentation with the kit, all of which only discusses SWDIO and SWDCK. XRES and VTarget are only mentioned in reference to JTAG.


                Perhaps this could be corrected or updated in future revisions?


                So, SWD debugging requires the following connections in order to work :

                1. SWDIO
                3. SWDCK
                5. XRES
                7. VTarget; and, of course,
                9. GND

                Optionally, SWV may also be required.


                I guess for me the choice is to use JTAG and have the ability to perform boundary scans, or SWD and not worry about boundary scanning.


                I'll take the risk and go with the non-boundary-scan option, if only because it means less re-routing!


                FWIW, the processor I replaced (eZ80F91) truly required only two signals, TCK and TDI, along with ground of course. I guess that's why I was confused by Cypress' reference to two-pin debugging - I assumed they meant two pins like Zilog meant two pins! Ah well, I learn something new every day!


                I hope this helps others who may be in the same boat!


                Cheers (and thanks again for the great support)