5 Replies Latest reply on Jun 3, 2011 6:35 AM by wayne.holloway

    PGA Output 0V-2.6V with VDDA at +5V


      I am using three PGA's a project to buffer R/C filtered PWM outputs.  All are configured with a gain of 1.  I am using a CY8C3866PVI-021ES2 for the development.  The problem PGA has input on P2_6 and the output on P2_4.  If I bypass the PGA with internal routing I see the signal on P2_4 range from about 0V to about 5V as expected per the PWM output.  If route through the PGA the maximum output voltage is about 2.6V.  I connected a VDAC8 to the PGA input and saw about the same results.  I get a slightly higher output when the PGA power is increased.  Is this an ES2 problem or a Creator problem?


      Placement looks like this:


      @[Chip=0][FFB(SC,2)]: \PGA_0_10:SC\





















          @[Chip=0][FFB(SC,0)]    :     \PGA_4_20:SC\   

      I tried to force other usage with the directive


      PGA_4_20:SC ForceComponentFixed F(SC,1) but it was ignored during synthesis.  Any ideas?

        • 1. Re: PGA Output 0V-2.6V with VDDA at +5V
          • Could you throw some light on the characteristics of  the PWM. What is the frequency of the PWM signal. The PGA is operation is limited by the GainBandwidth Product. PSoC3's PGA has a GainBandwidth Product of 7Mhz.
          • Also could you tell us the reason why you have used PGA, is it for buffering alone. The SC/CT based PGA is not capable of sourcing enough current as much as an Opamp on PSoC does. 
          • Could you provide a snashot of your topdesign or attach your project here.
          • 2. Re: PGA Output 0V-2.6V with VDDA at +5V

            This has to be a PGA/configuration issue or hardware.  Both the input and output RC filters are 39.4K/0.1uF.  When 4095 is written to the PWM the PGA input is 4.95VDC.  The PGA output rails at about 2.95V whether the PGA input is the VDAC or filtered PWM.  I don't believe loading is the issue since there is essentially no attenuation if the PGA is bypassed, and the series resistor on the output is 39K.  The specified DC load is actually about 2G ohm, so it looks like an open circuit.  The PGA output measures in excess of a megaohmto both the 5V rail and ground.  Screen shots of the top design and pinout are attached.  The results are the same whether the mux connection is present or removed.

            • 3. Re: PGA Output 0V-2.6V with VDDA at +5V

              More Info:


              I routed the PGA output to P0[2] and the Mux connection, but left P2[4] disconnected internally.  The PGA output would then go to 4.95V.  I then connected P0[2] to P2[4] external to the chip (and to the rest of the circuit).  The PGA still works properly.  For some reason the PGA output will not go to the positive rail when routed internally to P2[4].  Is there any way to fix this without changing the circuit board? 

              • 4. Re: PGA Output 0V-2.6V with VDDA at +5V

                This could probably be due to some routing issues. Could you attach your project so that we can look in to this and fix the issue.

                • 5. Re: PGA Output 0V-2.6V with VDDA at +5V

                  The attached project has the PGA's bypassed.  The proprietary 'C' source has been removed, but  I can put a complete generic project together if required.


                  The target design had the PGA's connected directly to the adjacent output pins, which is what you will need to do to troubleshoot the problem.


                  The previous iteration resulted in the problem moving from the Filt_4_20 output to the Filt_0_10 output, so nothing really got fixed.


                  Is any guidance available on how to troubleshoot/fix routing problems using the Directive tab for the cofiguration?


                  You asked why I'm using the PGA's instead of dedicated opamps.  The opamp loading is minimal, the dedicated outputs are already configured as ATD inputs, and I need three opamps.  Only two dedicated opamps are available on the package.

                  • 6. Re: PGA Output 0V-2.6V with VDDA at +5V

                    I received production silicon yesterday, and installed and tested it this morning with the pins added for debug and work-around removed from the project.  The problem no longer appears, so the problem apparently was either the ES2 silicon or Creator support for the ES2 silicon.