Please let me know what is the timing which you want to generate from Timer8 block. You want to source a clock of 250Hz to Timer8 block. There are a couple of solutions for this:
1. If operation of UART and Timer8 block is mutually exclusive: In this case, whenever you want to use Timer8, at that time you can modify the VC dividers to generate a clock of required frequency. But you cannot change the SysClk, so clock of Timer8 should be sourced from some other module and when UART has to be used VC dividers should be switched back to the normal mode. Please note that both of them cannot work simultaneously.
2. If both of them are supposed to work together, then you'll need another block which should divide the VC dividers to a required clock and then source it to Timer8 block. This would depend on the number of digital blocks your device have.
As far as I know you can't change SYSCLK, you can only change CPU_CLK's divider.
If you're trying to generate a 250Hz clock for your timer8 you can't do it that way. The lowest value you can get from VC3 is 366Hz. You're either going to have to use two timers, a 16-bit timer or do some division in an interrupt and bit-bang whatever output the timer is supposed to drive.
The good news is that leaves VC3 available for the UART. :)