The questions in this posting seem to have been answered through the Cypress tech support channel. I am posting answers here for completion.
Pullup on CS/ pin in SPI nvSRAM:
The Chip Select pin (CS/) should be driven by the controller during normal operation. During power up, it is possible that the controller pin would be floating when it is booting up. In case the controller boot up time is more than the nvSRAM boot up time (tHRECALL = 20ms), if the floating controller output presents a low to the pin, the nvSRAM chip is selected. To ensure that the chip is not selected, it is recommended that the CS/ pin is pulled up. This would avoid any undesired commands due to noise during these conditions.
Pullup on WE/ pin in parallel nvSRAM:
Similar to the above. If the controller pins connected to the WE/ and CE/ pins are floating during power up, and if nvSRAM is booted up, an unintended write can happen if the floating pins present low logic levels at WE/ and CE/ pins. Such an undesired write would corrupt the SRAM location, possibly in the first location (location depends on the levels in the floating address pins). To prevent this situation, a pull up is recommended on WE/ pin.
Pullup on HOLD/ pin in SPI:
HOLD/ pin is active low. Hence a pull up is recommended if this feature is not used in applications, to ensure Hold is not asserted. Even in application where Hold feature is used, it is a best practice to have this pull up in place.