2 Replies Latest reply on Jul 28, 2011 1:06 PM by anish.bhide

    Reducing Code Spread on ADC DelSig Measurements

    anish.bhide

      Hi,

         

      Im having difficulty reducing the code spread on a simple DC voltage measurement using the Delta Sigma ADC on the PSOC 5 CY8C5588AXI-060 my simple test is outputting the converted codes via UART to my PC to examine the results. DC Voltage measurements are yielding code values with spreads from 50-200 codes!

         

      I have tried passing the results through an FIR Filter, as well as using an external voltage reference and external clock source. I have even tried to use a Bypass decoupling capacitor on the internal voltage reference as the data sheet said this may help. The code spread improves slightly when the FIR filter is used:

         

      ADC Configuration: MultiSample (Turbo), 16 Bit Resolution, 1000 SPS, VSSA - 2.048, Bypass Buffer

         

      Filter Configuration: 1 ksps, 1 Filter Stage, Blackman, Lowpass, 120 Taps, 0.1 kHz, Data Ready Signal on Interrupt Request.

         

      @1.2 V input to the ADC taking 1000 Samples

         

      No Filter, Internal VREF (1.024): 380000 - 38100

         

      Filter, Internal VREF (1.024): 37980 - 38060

         

      Filter, Internal VREF (1.024), External Clock (250 kHz): 38120 - 38180

         

      Filter, Ext Vref (1.024), External Clock (250 kHz) 38120 - 38165

         

       

         

      My main issue is that i have no benchmark to compare against! How low is the ADC code spread actually capable of going on a simple measurement such as this? is there an optimal configuration for reducing this?

         

      Thanks for your help!

        • 1. Re: Reducing Code Spread on ADC DelSig Measurements
          david.ron

          Fdszh,

             

           

             

          A code spread of 50-200 looks strange.

             

           

             

          Which board are you using for the measurement? Is it a custom board built by you or a kit supplied by Cypress.

             

           

             

          Routing path plays an important role in Analog performance.

             

          Also, what is the source of 1.2V you are using? If you are using a pot for this, then a noisy pot will give a wide spread in code.

             

          If you are using CY8CKIT-001, then using Vadj will be a better option for testing as it provides a low noise analog output.

          • 2. Re: Reducing Code Spread on ADC DelSig Measurements
            anish.bhide

            Hi David,

               

            Thank you for your response!

               

            Im using the Cypress CY8CKIT-001 with the PSOC 5 for the measurement.

               

            To Supply the 1.2 V to the input of the ADC, im actually using an Audio Precision DCX-127. I use this for supplying both the ADC input votage, as well as an external reference voltage of 1.024. This is the most accurate and stable voltage source i have available to me.

               

            I've attached a graph of my best possible test data so far and the configuration is as follows:

               

            ADC Configuration: MultiSample (Turbo), 16 Bit Resolution, 1000 SPS, VSSA - 2.048, Bypass Buffer

               

            Filter Configuration: 1 ksps, 1 Filter Stage, Blackman, Lowpass, 120 Taps, 0.1 kHz, Data Ready Signal on Interrupt Request.

               

            External VREF (1.024): Audio Precision

               

            External Analog Clock: Clocktype "New" / Source "Auto"/ Frequency "100 kHz"/ tolerance -1% -> 1%

               

            Is this graphed data reasonable, or are better results from the ADC usually expected?