slfifosync SDK example question

[Anonymous]

Hello,

   

i want to use the slfifosync SDK example with 8bit parallel data bus width.

   

Do I have to configurate something inside the source code for this?

   

Best regards

   

g.

[Anonymous]

Hi g,

   

Please do the following,

   

1. In cyfxslfifogpifdscr.c file change the following line from

   

     {CY_U3P_PIB_GPIF_BUS_CONFIG_ADDRESS  , 0x000018a7},

   

   to

   

   {CY_U3P_PIB_GPIF_BUS_CONFIG_ADDRESS , 0x00001803},

   

This changes the GPIFII configuration Data bus width setting.

       

2. The address pins A[0] and  A[1] need to be connected to GPIO[8] and GPIO[9] instead of GPIO[28] and GPIO[29].

       

Regards,

   

Manish Rao

[Anonymous]

Is it also possible to run the Slave FIFO interface in 32 bit mode?

[Anonymous]

Hi Chris,

   

Yep. The 32 bit Slave FIFO support is being worked on. It will be incorporated in the next version of the SDK.

   

Regards,

   

Anand