This paper presents PSoC design aspects that enable users of PSoC devices to implement low power systems. It explains PSoC power modes and maps the power modes to design elements. It touches upon the UPF (Unified Power Format) that enables designers to concisely capture the system power architecture. The main focus of this paper is on low power concepts that relate to shutting down power to blocks in a chip. These general techniques are applicable to any SoC (System on Chip) and not necessarily to a PSoC. Read the full article here.