7 Replies Latest reply on Dec 28, 2017 4:17 AM by geethadiwakargeetha_2778001

    Missing data with Synchronous Fifo Firmware

    laim.maskey

      Hi,

         

      I am running the synchronous slave fifo firmware in 16 bit GPIF bus mode. I am using an FPGA to write data to the FX3 and to supply the SLWR signal, PCLK at 20 MHZ and monitor FLAGB to determine if the FX3 is full. The FPGA control/data sequence is as follows :
      If FLAGB is not asserted the FPGA brings SLWR low and sends an incrementing count over the GPIF data lines to the FX3. As soon as FLAGB goes low the FPGA brings SLWR high and stops incrementing the count. Using the Cypress Control Centre I can view the data transferred from the FPGA to the FX3 over IN endpoint 1. Everything  in this transfer seems fine until I cross a 1024 byte boundary where the next packet of 1024 has missed 8 bytes of data. For example if the first 1024 byte packet ended with the count value 1024  instead of seeing the next packet begin with the value 1025 it beings with 1029 - note each count is 2 bytes wide.

         

      I have run the GPIF bus in 32 bit mode and still see the same problem.

         

      Any ideas as to the cause of this?

         

      Thank you,

         

      Sodafarl

        • 1. Re: Missing data with Synchronous Fifo Firmware
          anand.srinivasan.asokan

           Which version of SDK are you using?

             

          When you say 8 bytes of data missing in the next 1024, is the "next packet" of 1024 bytes? If so, what are the last 8 bytes of this "next packet"?

             

          Regards,

             

          Anand

          • 2. Re: Missing data with Synchronous Fifo Firmware
            laim.maskey

            Hi,

               

            I am using the Beta2 version of the SDK - which I downloaded last week. The first packet of 1024 transfers correctly. The second packet has lost 8 bytes because the second packet count should start from 1025 but is now 1029. The last 4 counts of this second packet are out by 8 bytes - so instead of the last 4 counts (8 bytes) being 2045, 2046  2047,2048 they are now 2049, 2050, 2051, 2052.

               

            I've looked at the data and control between the FPGA nd the FX3 and it appears that the FLAGB  flag is asserting 8 bytes too late. 

               

            Regards,

               

            Sodafarl

            • 3. Re: Missing data with Synchronous Fifo Firmware
              laim.maskey

              Hi,

                 

              Problem solved regarding missing data. it was a combination of the FX3  fifo full flag latency which is three cycles and my FPGA code having one cycle latency when dealing with the full flag. The FPGA was only seeing the full flag  after  a delay of 4 pclock cyles and at two bytes per pclock transfer ( 16 bit wide bus) this amounted to sending 8 bytes to the fifo when it was already full. See this post for more detail on the flag latency http://www.cypress.com/?app=forum&id=167&rID=53201 

                 

               Are there any examples that show how to configure the full flag without this latency?

                 

               

                 

              Regards,

                 

              Sodafarl

              • 4. Re: Missing data with Synchronous Fifo Firmware
                geethadiwakargeetha_2778001

                i am facing this problem regarding flag and latency.....i am recieving 16 bytes zeros.and flags are not getting updated??

                • 5. Re: Missing data with Synchronous Fifo Firmware
                  mddd

                  There is no configuration of a full flag without latency, Either you can use a counter in the FPGA to stop the transfers or you can make use of the partial flags. For more details on how to configure the partial flags, please refer to the application note www.cypress.com/AN65974

                  • 6. Re: Missing data with Synchronous Fifo Firmware
                    geethadiwakargeetha_2778001

                    i am interfacing zynq(7000)fpga to fx3s(cyusb3035) with

                    slavefifo_2bit_address bus....can i change/modify verilog code provided by

                    xilinx app noteAN65974??

                    can i neglect flag a and flag b in the gpif2 designer tool??

                    r can i comment flag a and flag b in the verilog code??does it make sense??

                    because i tryed all possible configuration in gpif 2 designer tool for flag

                    a and flagb??its not updating properly please help me??

                    flaga.png........>>>i am using flag a as

                    flagb.png........>>>i am using flag b as

                    fpgablock.png....>>>this is my fpga block diagram(zynq 7000 series)

                    verilogcode.png.....>>>this is the veriolog code.they are checking flag a

                    and flag b status to write data to fx3

                    one time i am going to recieve the data??next time fpga stops writing to

                    fx3 because write signal is going high....

                    but flags are not getting updated???this is my problem??please help me

                    • 7. Re: Missing data with Synchronous Fifo Firmware
                      geethadiwakargeetha_2778001

                      before1.png........>>>before i run fx3(EZ-USB).....data is coming from the

                      fpga(zynq70z20)

                      if run fx3......i am not getting data in the controller centre.its showing

                      error997(bulkerror.png)

                      after.png........>>>this is the result after running fx3s

                      chanelcreate.png.........>>>this is how i am creating channel

                      please help me i am suffering from last 4 months.i am not getting where is

                      the problem??

                      do i need to attach whole project??

                      do i need to read more on????

                       

                       

                      On Thu, Dec 28, 2017 at 3:08 PM, geetha diwakar <