2 Replies Latest reply on Aug 25, 2011 10:11 AM by userc_44516

    Byte Qualifier on Slave FIFO Interface



      I've got a question concerning the "Synchronous Slave FIFO interface with 32-bit data bus". It’s the interface between the FX3 and a FPGA in our application.  I’m wondering what happens if the USB packet length is not a multiple of 4 that means it fits not completely to the 32 bit bus width.
      During the read sequence (from FX3 to FPGA) the last 32-bit-word that is read from the FX3-FIFO will contain less than 4 bytes. Therefore the FPGA doesn't know which bytes of the last word are valid. On the other hand during the write sequence (from FPGA to FX3) the last 32-bit-word that is written to the FX3-FIFO will contain less than 4 bytes. In that case the FX3 doesn't know which bytes are valid. I think there must be a kind of “byte qualifier” signal to mark the valid bytes within the 32-bit-words. Is it possible to configure some flags in the GPIF II as “byte enable”? I didn't find any hint in the application notes.


      Best regards...