7 Replies Latest reply on Sep 14, 2011 4:16 AM by gayathri.vasudevan

    Packet not commited on fx2lp

    mirza.pasovic

      Hello everybody

         

       

         

      i am new here and this is my first post so please be patient with me.

         

       

         

      I am using fx2lp (cy7c60813A) for transfering images from my camera. As a master i use FPGA Cyclone3. Now, i have setup everything and implemented (adjusted) a state machine in VHDL for bulk transfer of data. I am using the EP2,EP6 and EP8 configuration from TRM (i think it is number 4). It is valid. I should also point out that the configuration i am using worked previously just fine. Yesterday i had to re-install my system. So i deleted everything and install WinXp (32-bit) and cypress driver (3.4.5). I downloaded my FPGA configration, and any transfere i try always endups in timeout.

         

       

         

      I decided to follow things with signal tap and the logic is ok. I also hooked up my scope on FullFLAG and it is always HIGH (the USB FIFO never goes full) My USB_CS, USB_WR and USB_OE pins are LOW during writing procedure while USB_RD is high. Fifo ADDRESS is set to '00' (endpoint 2). Now when i start CyConsole the device is recognized with all configurations properly initialized. In my application i use CyApi and i can read my device, configraion and enpoints with no problem. BUT TRANSFER OVER THOSE NEVER HAPPENS. I just do not understand what is happening. I also dont know what eles too try.

         

       

         

      I tryed the bulkloop example provided by cypress and it works fine. My application also worked fine before i reinstalled my system. I have installed the drivers i used in previous times, but nothing works. Please tell me what can i do, what should i try what should i look for in moving ahead.

         

       

         

      kind regards

         

       

         

      mirza