That's a really good question!
You can still use 1024 cycles as a minimum PLL Lock time for our 65 nm products.
In this specification, Cypress surpasses the QDR consortium specification for PLL lock time (tKC lock) of 20 µs (min. spec.) and will lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version.
But in the future higher speed designs, it won't be the same as 1024 clock cycles or 20 uS.