Please let me know why would you expect the GPIO to be synchronous with the clock source especially given that the internal core runs at a higher frequency than the clock source? Please let me know the reason behind this synchronous requirement.
The FX3.0 is suppose to transfer data (8-bit) to an FPGA using GPIO. In order to be able to transfer data we provide them two synch clocks. So the clocking on the GPIO have to be synch with this clock so that FPGA can receive the data.
If you want to use a bus architecture then you've to go with GPIF II. If you use the GPIO then you'll be setting one at time and there will be a time difference even between each of the GPIOs. Have you taken this into account.
The 19.2, 26 MHz etc is the clock source for the internal clock mechanism. It is hard to comment in terms of time synchronization for a GPIO. You can find the timing diagram of the GPIF II interface in the datasheet and app notes. Please let me know why you are trying to implement a 8-bit bus using GPIO rather than the GPIF II interface.
I use both GPIF and GPIOs for communicating between USB FX3 and FPGA.
The GPIOs are in two groups:
1. some are used to configure the FPGA
2. the rest are used for sending and receiving commands and small byte of data for example to set-up the paths of data for the large which are transferring throuhg GPIF
I will use the GPIF as slave synch FIFO. This is the method I used with FX2LP IC and worked just fine. Is there anyway I can reue my desing for the FX3.0?