maybe you would say there are no pin in the sysmem , but it is accessed by multiple peripheral block simultaneously. so i can't understand the course.
@ Data Flow:
DMA 1 [FIFO -> Socket, DMA Controller, Thread -> DMA-AHB -> Bridge -> ARM-AHB -> Sysmem]
DMA 2 Just the same of DMA 1, chain may reversed.
@ AHB bus freq may be 200MHz @ 32Bits. The 200MHz ARM926 Core hits for that.
@ System Memory can be Accessed by ARM Core, DMA Controllers in Time Divided pattern.
If the AHB Bus speed and System Memory working freq are high enough, bandwidth is OK.
@ DMA access may use burst mode, please refer SlaveFIFO demo on DMA transfer settings.
Also, please refer ARM AHB/AXI bus specifications.
@ Data flow is controlled under DMA controller for xfer between Peripheral and Sysmem.
There may be many DMA controller so that they working in parallel.
Programmer Manual, DMA section said sth. on this.
@ DMA Controller read descriptor from Sysmem and do data xfer according ot the descriptor.
So please get some ARM core MCU with DMA specs to understand how is DMA working.
And also, ARM official site provide Bus, Core and DMA docs for your reading.
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