1 Reply Latest reply on Nov 3, 2011 10:29 PM by anand.srinivasan.asokan

    8-Bit Parallel MPEG2-TS transfer at slave fifo autoin mode   lose package

    youka.ji

       Hi,all

         

      MPEG2-TS------>CY7c68013------>PC 

         

      recently,i am doing a job which mpeg2-Ts stream Transferred to a computer.i used cy7c68013a-56 chip,endpoint2 bulk in 4xbuffer.Frimware,i reference to http://www.cypress.com/?rID=39714

         

      my question is:

         

      When I received the usb pass over the data and stores it into a TS file, i found about 1/3 data lost.

         

      Driver:          ezusb.sys

         

      frimware:

         

       

         

      CPUCS = 0x10; // CLKSPD[1:0]=10, for 48 MHz operation

         

      SYNCDELAY;

         

      REVCTL=0x03;

         

      IFCONFIG = 0xCB; // IFCLK Source internal (i.e.) Gated MPEG_CLK,  MPEG_CLK is connected to SLWR

         

      // FX2LP in SLAVE FIFO Mode

         

      SYNCDELAY;

         

       

         

      FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions

         

      SYNCDELAY; // see TRM section 15.14

         

       

         

      FIFORESET = 0x82; // reset, FIFO 2

         

      SYNCDELAY; //

         

       

         

      FIFORESET = 0x84; // reset, FIFO 4

         

      SYNCDELAY; //

         

       

         

      FIFORESET = 0x86; // reset, FIFO 6

         

      SYNCDELAY; //

         

       

         

      FIFORESET = 0x88; // reset, FIFO 8

         

      SYNCDELAY; //

         

       

         

      FIFORESET = 0x00; // deactivate NAK-ALL

         

      SYNCDELAY;

         

       

         

      PINFLAGSAB = 0x00; //

         

      SYNCDELAY;

         

       

         

      PINFLAGSCD = 0x00; //

         

      SYNCDELAY;

         

       

         

      PORTACFG = 0x00; //

         

      SYNCDELAY;

         

       

         

      FIFOPINPOLAR = 0x04; // SLWR is configured as active HIGH : Can be changed to 0x00 for SLWR to be active Low

         

      SYNCDELAY;

         

       

         

      EP2CFG = 0xE0;   // VALID - 1,DIR - IN,Type- Bulk, Size - 512 Bytes, Quad Buffered 

         

      SYNCDELAY;

         

       

         

      EP4CFG = 0x00; // clear valid bit

         

      SYNCDELAY; //

         

       

         

      EP6CFG = 0x00; // clear valid bit

         

      SYNCDELAY; //

         

       

         

      EP8CFG = 0x00; // clear valid bit

         

      SYNCDELAY;

         

       

         

      EP2FIFOCFG = 0x08; // AUTO IN, NO Zero Length Packets, 8- bit Wide 

         

      SYNCDELAY;

         

       

         

      EP2AUTOINLENH = 0x02; // Auto-commit 512-byte packets

         

      SYNCDELAY;

         

       

         

      EP2AUTOINLENL = 0x00;

         

      SYNCDELAY;

         

      OEA |= 0x30;

         

      IOA &= ~20;

         

       

         


      I beg your reply......