4 Replies Latest reply on Nov 12, 2011 2:55 PM by userc_44433

    Two cycle latency of full flag in slave fifo example



      We are designing FPGA to write data to FX3 Synchronous Slave FIFO. Our FPGA use thread 0 (A0,A1 = 00) and monitor FLAGB pin for FIFO full status. For firmware we use SlaveFifoSync example provided in SDK.


      In application note AN65974[Designing with the EZ-USB FX3 Slave FIFO Interface], it mention that there are two-cycle latency incurred in current thread flag.


      So we try to configure the FLAGB as dedicated thread flag for thread 0. What we modified is to change


      {CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(5)      , 0x00000018}, // FLAGB as the  current thread  flag




      {CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(5)      , 0x00000010}, // FLAGB as the  dedicated thread 0 flag


      However, the two cycle latency are still exist after we apply this patch...




      Is there any solution available to configure full flag without the latency?