2 Replies Latest reply on Nov 16, 2011 5:42 AM by gautam.das.g

    Status and controll registers usage

    pasquale.de.sando

      I'm trying to implement a VME interface using a PSoC devices, but there are some things I would know.

         
            
      • How a status and controll register are accessed from uC ?
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      • For example, If I use two 8bit status registers for reading a 16bit data bus, using the cortex-M3, the reading will be performed contemporarily or it needs two or more clock intervals?
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      • How they are mapped on PSoC?
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      • What type of internal bus they use?
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      • Could I associate the same variable at two or more status or controll registers?
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      • There is a way to choose to use the FIFO registers contained in the UDBs or it is the IDE that assign the internal resources?
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      Thanks in advance

        • 1. Re: Status and controll registers usage
          ki.leung

          Your question involves understanding of how PSoC works. I suggest you go and download some simple projects to see how the internal stuffs works with PSoC, try a few examples should help you design what to do.

          • 2. Re: Status and controll registers usage
            gautam.das.g

            Hi PDES,

               
               

             

               
               
                  
                  
            • Control Register is used to control the digital system by the CPU. You can use the APIs      _Write( ); a Status Register is used when the CPU needs to read the status of internal digital signals. The API used for this is      _Read( )
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            • There are Universal Digital Blocks (UDB) in PSoC3/5 which has a Status and a Control Register each. When a 16-bit parallel digital signal is to be read, then two Status Registers from two UDBs will be utilized. These has to be read as two 8-bit data by the CPU.
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            • A PSoC3/5 can have a max of 24 UDBs. It depends on the part number used. Hence there are equal number of Status and Control registers as the number of UDBs present. For more details on the placement of these registers refer to the UDB section of the Technical Reference Manual (TRM) here http://www.cypress.com/?docID=31882
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