1 Reply Latest reply on Nov 17, 2011 11:13 PM by aju

    VHDL Model in Xilinx ISIM


      I am attempting to simulate a cy62157ev30 interface coded in verilog and using the VHDL model provided by Cypress.  I will attach an image of the module (mobl_512kx16) waveform in simulation.  I am not sure what I am doing or if it is a software problem with the simulator, but I would appreciate it if someone could look at the timing (behavioral logic) and see if I am doing something wrong -- this is a write cycle...   I am not sure why the data_skew is undefined.