While I was debugging my logic that interfaces to the FX3, I noticed something I would like to confirm. We are using Synchronous Slave FIFO Write Mode of the FX3 GPIF-II.
According to the FX3 spec (CYUSB3014.pdf page-21), there are two different ways of issuing PKTEND, one with last data and one without data (ZLP). Unlike FX2, FIFOADDR must be presented a cycle earlier to write data.
In the first case (PKTEND w/ data) PKTEND seems assocating with the address the write data is associating with, which is the address in the previous cycle. However, in the latter case (PKTEND w/o data) the PKTEND is associating with the address in the same cycle.
As my design pipelines the address and the data, the address in the last data cycle *may* not stay the same from the previous cycle.
I would like to know whether the PKTEND in the first case (PKTEND w/ data) is associating with the address in the previous cycle or the address in the cycle that is coincident to the write data.
If the PKTEND is associating with the address in the same cycle, Cypress should mention such restriction in the FX3 documentation. Otherwise, it would create a hard-to-debug mysterious problem.
Thank you for your attention.
In page 22 there is a explanation which explains that state of FIFOADDR pins as well while using PKTEND pin. Please clarify which part of it is not clear.