5 Replies Latest reply on Dec 2, 2011 7:05 AM by gautamd_

    designing own components

      Is it possible to create a 24 bit ADC in psoc 5, if so how? In the same way can we use VHDL besides verilog to build our own components in PSOC 5. 


      I have a doubt regarding EMIF, can we interface a 16GB external memory to psoc 5 devices

        • 1. Re: designing own components

          Hi Srinath,




          1) Is there any specific reason you want to get 24-bit ADC?


          2) Only Verilog is supported for creating Custom Components in PSoC Creator.


          3) PSoC supports EMIF interface. The EMIF supports four types of external memory: synchronous SRAM, asynchronous SRAM, cellular RAM/PSRAM, and NOR Flash. The EMIF generates external memory control signals only for synchronous SRAM; these signals can also be routed to UDBs for use with the other types of memory. External memory can be accessed via the 8051 xdata space or the ARM Cortex-M3 external RAM space; up to 24 address bits can be used. The memory can be 8- or 16-bits wide.

          • 2. Re: designing own components

             yes i need to have an ADC with 24 bit wide, Is it possible to synthesize in Psoc 5

            • 3. Re: designing own components
              • May be you can reduce the ADC reference to a small value to measure smaller voltages. But noise will start playing a big role in that case. Typically noise in most of the boards will be in the uV range. Even if you have a 24 bit ADC, your board design is going to play a big role.
              • I dont think it is possible to sunthesize ADC. ADC is a complex block and it is very difficult to synthesize such a block. In PSoC5 you get two DelsiG ADCs with 20 bit resolution.
              • 4. Re: designing own components

                A 5V range 24bit ADC has a resolution of 0.3uV per bit. Unless you have a very clean power and singal and a stable reference, the extra bits are meaningless. 

                • 5. Re: designing own components

                  Hi Srinath,




                  As lleung has already mentioned, even if you intend to use a 24 bit resolution ADC, the ENOB (Effective Number Of Bits) which you'll receive will be lesser and will depend upon the noise.


                  You can average out the samples obtained to get better values. However this has a disadvantage that the data rate will be reduced.