3 Replies Latest reply on Dec 15, 2011 11:33 AM by kannan.sadasivam

    PSoC 5 ADC's Voltage Ref

    alex.b

      Hello All,

         

      With the 2*VDAC Vref sourcing option, can you apply low voltages to the range? For example, with the VDAC, it is theoretically possible to set the range to 8mV (4mv*2). I would assume that this would probably cause a lot of noise, or cause a major reduction in SINAD. It seems that we also have to use external decoupling capacitors too.

         

      If this is the case, what is the lowest range that we can set using the VDAC and still get good results? For example, would setting the VDAC to 0.512V give it a good performance range of 1.024V (0.512V*2)?

         

      Any clarification would be helpful.

         

      Alex

        • 1. Re: PSoC 5 ADC's Voltage Ref
          user_37926942

           That is a good question. It looks like in the current PSoC parts, the lowest designed range is 1.024V. The question for you is wether lower ranges will even work.

          • 2. Re: PSoC 5 ADC's Voltage Ref
            kannan.sadasivam

            On the kits like Kit-030 a user could easily solder the refernce capacitor on the protoarea. I believe both the reference pins for the SAR ADC are brought out in to the proto space.

            • 3. Re: PSoC 5 ADC's Voltage Ref
              kannan.sadasivam

              Oops ignore the previous post it was a mistake. Intended to post in another topic.

                 

              But about the use of the VDAC reference. Theoritically the VDAC might be able to achieve a range as low as the least count of the DAC but we have to understand that there are lot of factors of the reference that affects the ADCs performance.

                 

              For one, there is the DACs noise which would be adding in as a reference noise. The output noise is the same floor at any code whereas the ADC is ratiometric to the reference. Which means at the lower values of the reference this noise might have a dominant effect. There could be a serious effect on ENOB.

                 

              Also any linearity errors that the DAC might have would manifest into linearity and gain errors in the ADC.

                 

              I would also be worried about the effect on the bandwidth due to the use of the VDAC since its a high output impedance system.

                 

              Though this has not been brought out in the datasheet, a user, I believe should expect some performance degrdation in this case.