The DMA controller in PSoC® 3 and PSoC 5 is used to handle data transfer without CPU intervention. AN52705 - PSoC® 3 and PSoC 5 - Getting Started with DMA provides an overview of DMA in PSoC3/5 and information on different ways to configure the DMA channels o perform data transfers.
The DMA can be very useful in applications that require ADC data buffering and allows the CPU to do other tasks simultaneously. The Delta-Sigma ADC has programmable resolutions from 8-bits to 20-bits. This ADC output is available in 32-bit format consisting of four 8-bit registers: OUTSAMP, OUTSAMPM, OUTSAMPH, and OUTSAMPS registers. The OUTSAMPS register gives sign extension of the data if OUTSAMPH is read as a 16-bit register. In the default ADC configuration, the output is aligned to the least significant bit (LSB). Hence for an n bit resolution, the ADC result is always available in the least n bits starting from OUTSAMP.
8-Bit ADC Data Buffering Using DMA
For 8-bit ADC data buffering, the contents of OUTSAMP register should be moved to memory buffer on each EoC (End of Conversion) signal. The ADC generates an EoC signal at the end of each conversion, which can be used as the DMA channel trigger to buffer the ADC data. The block diagram illustrating 8-bit transfer is as follows.
AN61102 PSoC3 and PSoC5 ADC Data Buffering using DMA provides a detailed example project implementing the above block diagram. The application note also explains basics of 16-bit, and 20-bit Delta-Sigma ADC data buffering using DMA with example projects. The 20-bit example project accompanying this application note demonstrates problems with data buffering using DMA and how to tackle this using multiple DMA channels. The application note also includes an example project on 12-bit SAR ADC data buffering for PSoC 5 device.
Please access the application note webpage to download the document and zip file containing the example projects. Note that these are all updated to work with PSoC Creator 2.0, the latest edition of our PSoC Creator software.