All DMA need at least 3 signals:
Request A DMA Cycle is needed and requested.
ACK The current DMA cycle is comple.
Finished the count of DMA cycles is complete
ok you could also have terminate which is supported.
I am finding that the lack of ACK signalling to be a deal breaker with external devices. I have to create a Slave port to I2S output device and was thinking of using the PSOC3 for this. But I cannot seem to find anyway to know when the current DMA cycle has actually read (ACK) the port. So for my case it looks like this:
Req-> into the PSOC3, indicating DATA ready
<-ACK indicating that the PSOC3 has read the DATA and ready for the next Req.
Any ideas? I would also like to see more of the 16 bit access that is talked up in the data sheets and the uTube video.
For your ACK signal, you actually only need a delayed request signal. One could either use a PWM for driving the clock signals, or use a counter for creating the delayed signal.
If your request signal is created externally, I think one could build a small state machine out of a clock and a LUT. Since the DMA timing is static, this should work. If you use a status register for buffering the incoming data, the actual timing of the DMA should not matter, since you can control the register directly.