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PSoC®3 and PSoC®5 devices feature a Direct Memory Access (DMA) engine, which can used for data transfer between on-chip elements without any CPU intervention. The DMA engine is part of a high performance bus known as the peripheral hub (PHUB). The PHUB is a programmable and configurable central bus backbone within PSoC3/PSoC5 devices that ties the various on-chip system elements together. It consists of multiple spokes; each spoke is connected to one or more peripheral blocks.
The DMA with the help of Transaction Descriptors (TD) can move data from a source to destination at very high speeds. The TDs can be chained together to perform complex data transfers. The following diagram illustrates a simple data transfer using DMA.
The key features of PSoC® 3 and PSoC® 5 DMA are:
- 24 DMA channels
- Each channel has one or more Transaction Descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be defined
- TDs can be dynamically updated
- Eight levels of priority per channel
- Any digitally routable signal, the CPU, or another DMA channel, can trigger a transaction
- Each channel can generate up to two interrupts per transfer
- Transactions can be stalled or canceled
- Supports transaction size of infinite or 1 to 64k bytes
- TDs may be nested and/or chained for complex transactions
Please refer AN52705 - PSoC® 3 and PSoC 5 - Getting Started with DMA for information on different ways to configure the DMA channel and TD to perform data transfers. The application note also has example projects and a brief video.
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PSoC 3
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Dasq,
All DMA need at least 3 signals:
Request A DMA Cycle is needed and requested.
ACK The current DMA cycle is comple.
Finished the count of DMA cycles is complete
ok you could also have terminate which is supported.
I am finding that the lack of ACK signalling to be a deal breaker with external devices. I have to create a Slave port to I2S output device and was thinking of using the PSOC3 for this. But I cannot seem to find anyway to know when the current DMA cycle has actually read (ACK) the port. So for my case it looks like this:
Req-> into the PSOC3, indicating DATA ready
<-ACK indicating that the PSOC3 has read the DATA and ready for the next Req.
Any ideas? I would also like to see more of the 16 bit access that is talked up in the data sheets and the uTube video.
Thanks
Gordon
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For your ACK signal, you actually only need a delayed request signal. One could either use a PWM for driving the clock signals, or use a counter for creating the delayed signal.
If your request signal is created externally, I think one could build a small state machine out of a clock and a LUT. Since the DMA timing is static, this should work. If you use a status register for buffering the incoming data, the actual timing of the DMA should not matter, since you can control the register directly.