The datasheet states "The DMA generates a pulse of width two bus clocks at the
nrq when the DMA transfer is complete." This means the end of the whole TD.
I suggest you read the app note about the DMA (see http://www.cypress.com/?app=forum&id=2492&rID=53352 ) and the one about interrupts (see http://www.cypress.com/?app=forum&id=2233&rID=57231 ). Especially the latter one will be important for you, because the UART component doesn't create an interrupt per byte received, but stays high as long as a byte is in the receive buffer. You will need to take that into account.
I had seen that sentence but didn't know how to interpret it. If someone reads this who is in charge of the app note, adding a phrase to explain that might be helpful to the next person.
I hadn't realized the UART byte received interrupt would stay high. This shouldn't be a problem if I set the DMA component's "Hardware Request" property to "Level", though, if I understand correctly. Thanks for the heads up.
The proper explanation is hidden in the description of the TD_TERMOUT_EN flag - there it says 'when this TD completes'. If I think about it, this would mean if you have multiple TDs chained together, each one would (potentially) generate a trigger signal. I think it might be a good idea to add this explanation to the output signal (nrq) documentation.
I was not aware that the DMA could be trigger by a level signal - but it is actually what you need. Sounds like a good plan, then. Can you keep us informed when you got it working?