About Slave Fifo reset

[Anonymous]

I use a fx3 dvk to communicate with my fpga board in slave fifo sync mode. How can i clear the fifo before i begin an in  transfer. i have tried "CyU3PUsbFlushEp" "CyU3PUsbResetEp" and other channel functions but fifo still connot be cleared. I referred to the fx2 program:FIFORESET = 0x06.So can someone tell me the right funtion or give me some suggestion.thanks.

[Anonymous]

my fpga will write data into fifo because i connot stop it immediately,so i need clear the fifo befor a new transfer