10 Replies Latest reply on Jan 17, 2012 11:37 PM by gaya

    FX2LP: Slave FIFO gives alternating data values instead of expected data

    dan.morgan

       I am using the Slave FIFO to do bulk transfers from the host to an FPGA. When I send a packet from the host I am able to read the expected number of bytes from the Slave FIFO. However instead of the expected data I get an alternating sequence of bytes. Further, there are 2 sequences, which alternate with each packet sent.

         

      For example:

         
          The host sends a packet with 8 bytes -> (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07).   
         
          The FPGA reads 8 bytes ->  (0x42, 0xBE, 0x42, 0xBE, 0x42, 0xBE, 0x42, 0xBE).   
         
          The host sends a packet with 8 bytes -> (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07).   
         
          The FPGA reads 8 bytes ->  (0x67, 0x99, 0x67, 0x99, 0x67, 0x99, 0x67, 0x99).   
         
          The host sends a packet with 8 bytes -> (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07).   
         
          The FPGA reads 8 bytes ->  (0x42, 0xBE, 0x42, 0xBE, 0x42, 0xBE, 0x42, 0xBE).   
         
          The host sends a packet with 8 bytes -> (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07).   
         
          The FPGA reads 8 bytes ->  (0x67, 0x99, 0x67, 0x99, 0x67, 0x99, 0x67, 0x99).   
         

      And so on.

         

      The endpoint is double buffered, so maybe it switches between sequences when the buffer changes?

         

      I verified with a USB analyzer that the packet sent to the FX2LP is correct.

         

       Any ideas why I get these symptoms?

        • 1. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
          gaya

           Hello,

             

           

             

          In which mode are you using FX2LP ? Auto / Manual mode ? If in manual mode, are you not committing the FIFOs from FX2LP (inside 8051 firmware) ? Also if in manual mode, have you not armed the buffers initially (inside TD_INIT() ) ? If you can attach your code (TD_INIT and TD_POLL ), we can take a look, if something os missing.

             

           

             

          Regards,

             

          Gayathri

          • 3. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
            dan.morgan

            After looking in detail at other forum posts I found one which seems to have similar symptoms. A post near the end indicates that the poster is getting alternating values.

               

             

               

            However no answer is found. Maybe there is a tech support case related to the other thread?

            • 5. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
              james.wood

              SLOE is always asserted in our design (Master does not have control over this pin in our design). Is this ok?

                 

              TD_INIT:
                    SYNCDELAY; BREAKPT &= ~bmBPEN;      // to see BKPT LED go out TGE
                  // set the CPU clock to 48MHz
                     SYNCDELAY; CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);   


                  SYNCDELAY; IFCONFIG = 0xC0;   // use IFCLK pin driven by internal logic
                                       // for now don't enable slave fifo
                                       // fifo pins conflict with spi programming for fpga   

                    
                 
                  SYNCDELAY; REVCTL = 0x00;     // DYN_OUT=0, cpu bypassed for out packets 
                  SYNCDELAY; EP1OUTCFG = 0xA0;    // see TRM section 15.14
                 
                  SYNCDELAY;  EP1INCFG  = 0xA0;
                        

                  //disable other endpoints
                  SYNCDELAY; EP2CFG = 0x7f;
                  SYNCDELAY; EP8CFG = 0x7f;
                  SYNCDELAY; EP6CFG = 0x7f;
                 

                  SYNCDELAY; EP4CFG = 0xA0;     // sets EP8 valid for OUT's
                                       // and defines the endpoint for 512 byte packets, 2x buffered
                 
                  SYNCDELAY; FIFORESET = 0x80;  // reset all FIFOs
                  SYNCDELAY; FIFORESET = 0x02;
                  SYNCDELAY; FIFORESET = 0x04;
                  SYNCDELAY; FIFORESET = 0x06;   
                  SYNCDELAY; FIFORESET = 0x08;   
                  SYNCDELAY; FIFORESET = 0x00;
                   
                 
                  SYNCDELAY; EP4FIFOCFG = 0x10; // this lets the EZ-USB auto commit OUT packets
                                     // and sets the slave FIFO data interface to 8-bits
                 
                  SYNCDELAY; EP2FIFOCFG = 0x00;     //set all fifocfg to 8 bit interface so portd works     
                  SYNCDELAY; EP8FIFOCFG = 0x00;     
                  SYNCDELAY; EP6FIFOCFG = 0x00;
                   


                  SYNCDELAY; PINFLAGSAB = 0x00; // define all flags as indexed            
                  SYNCDELAY; PINFLAGSCD = 0x00;        
                 

                  SYNCDELAY; PORTACFG = 0x00;   // used PA7/FLAGD as a port pin, not as a FIFO flag    
                  SYNCDELAY;     FIFOPINPOLAR = 0x12; // set sloe active high, set empty == 1

                 EZUSB_InitI2C();
                 Initialize_Timer();

                 EA = 1;                          // Enable 8051 interrupts
                 I2CTL = bm400KHZ;
                
                 ////////////////////////////////////////////////////////
                 // Initialize Port D IO as SPI signal pins (SPI Flash Chip store FPGA code)
                 // We need this for Write/Read to SPI chip for FPGA reprogramming.
                 InitializeSPI();

                 /////////////////////////////////////////////////////////
                 // Reset FPGA register
                 // Just to hold FPGA in reset  
                 FPGA_REG_RESET_PORT    |=  FPGA_REG_RESET_REG_BIT;        // High - Reset FPGA
                
                 // Fetch data from SPI and send to FPGA
                 g_FPGA_Alive = FpgaCfgSerialMode(SVID_FPGA_BIN_SIZE);       

                 MillisecondDelay(500);
                 FPGA_REG_RESET_PORT    &= (~FPGA_REG_RESET_REG_BIT);    // Low  - out from reset
                 MillisecondDelay(500);
               
                 EA = 0;

                 OEB = 0;
                 SYNCDELAY; IFCONFIG = 0xCB; //enable slave fifo mode

                 

               

                 

              TD_POLL:

                 

                    empty...

              • 6. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
                gaya

                 Hello Dan,

                   

                 

                   

                Can you post the TD_INIT() part of your code ? since FX2LP is in Slave, AUTO mode, I believe there is no code in your TD_POLL (). Please confirm. 

                   

                 

                   

                Regards,

                   

                Gayathri

                • 7. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
                  gaya

                   Hello imwood,

                     

                   

                     

                  From the code that you had pasted, I could see that the endpoint configuration that you are using is not valid. The endpoint configuration that you should be using, should be one among the 12 valid configurations as is mentioned in section "1.18 EZ-USB Endpoint Buffers" in EZ-USB TRM. Please refer and correct the same. Then double check if it is working.

                     

                  (Are you also having issue similar to what Dan had posed above ?)

                     

                   

                     

                  Regards,

                     

                  Gayathri

                  • 8. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
                    james.wood

                    i am working with dan on the same cypress project. Thanks, I will take a look at the endpoint configurations....

                    • 9. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
                      dan.morgan

                      Thank You!

                         

                       

                         

                      The end point configuration was the issue...

                         

                       

                         

                      The problem is solved.

                      • 10. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
                        james.wood

                        that was the problem. I commented out these lines and it started working. Thanks!

                           

                         

                           

                            //disable other endpoints
                            SYNCDELAY; EP2CFG = 0x7f;
                            SYNCDELAY; EP8CFG = 0x7f;
                            SYNCDELAY; EP6CFG = 0x7f;

                        • 11. Re: FX2LP: Slave FIFO gives alternating data values instead of expected data
                          gaya

                           Hello Dan, imwood,

                             

                           

                             

                          Glad to hear that the problem is resolved now, and thank you for posting the solution here. It might help someone later.

                             

                           

                             

                          Regards,

                             

                          Gayathri