10 Replies Latest reply on Jan 17, 2012 11:37 PM by gayathri.vasudevan

    FX2LP: Slave FIFO gives alternating data values instead of expected data

    dan.morgan

       I am using the Slave FIFO to do bulk transfers from the host to an FPGA. When I send a packet from the host I am able to read the expected number of bytes from the Slave FIFO. However instead of the expected data I get an alternating sequence of bytes. Further, there are 2 sequences, which alternate with each packet sent.

         

      For example:

         
          The host sends a packet with 8 bytes -> (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07).   
         
          The FPGA reads 8 bytes ->  (0x42, 0xBE, 0x42, 0xBE, 0x42, 0xBE, 0x42, 0xBE).   
         
          The host sends a packet with 8 bytes -> (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07).   
         
          The FPGA reads 8 bytes ->  (0x67, 0x99, 0x67, 0x99, 0x67, 0x99, 0x67, 0x99).   
         
          The host sends a packet with 8 bytes -> (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07).   
         
          The FPGA reads 8 bytes ->  (0x42, 0xBE, 0x42, 0xBE, 0x42, 0xBE, 0x42, 0xBE).   
         
          The host sends a packet with 8 bytes -> (0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07).   
         
          The FPGA reads 8 bytes ->  (0x67, 0x99, 0x67, 0x99, 0x67, 0x99, 0x67, 0x99).   
         

      And so on.

         

      The endpoint is double buffered, so maybe it switches between sequences when the buffer changes?

         

      I verified with a USB analyzer that the packet sent to the FX2LP is correct.

         

       Any ideas why I get these symptoms?