5 Replies Latest reply on Jan 29, 2012 11:59 PM by GayathriV_16

    FX2LP Slave FIFO full and empty change simultaneously

      i'm using the slave FIFO interface for bulk auto-in transfers directly from an FPGA to the host, in asynchronous mode.




      Right after the FULL flag asserts, the FULL flag deasserts and the EMPTY flag asserts simultaneously.




      I have attached a screen shot of the waveforms.




      Any ideas of what could cause this?