The burst writes mentioned in the single queue HDFIFO CYF0018V datasheet indicate that the HDFIFO can be written to only in bursts of two. There is no such restriction on the number of reads(odd or even) performed on the HDFIFO. I request you to clarify if you are looking for any other specific information regarding the burst writes and reads to the device.
Thanks & Regards,
I take it from the answer to this question that there exists no VHDL model of the FIFO?
A model would be very useful as the part appears non-trivial, especially with all the latencies.