2 Replies Latest reply on Feb 6, 2012 12:47 AM by sridharm_

    See generated Verilog ?


      Hi all,




      When I place a digital component, and build the project, does that component generate a Verilog file ?  Is it possible to see this verilog file ?




      Many thanks


      Hugo Elias

        • 1. Re: See generated Verilog ?

          Hi Hugo Elias,




          You can view the Verilog source file of the UDB based components from the CyComponentLibrary.Lib.


          You can access this from your installation folder. In my case, the location turns out to be


          C:\Program Files\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib




          A word of caution! The C files, Header files and the Verilog files if manipulated here will change forever. The change done, if any, will reflect in the Creator generated files. However, you can view the Verilog file to understand its implementation.

          • 2. Re: See generated Verilog ?

            Hello Hugo Elias,


             As far as I know, There is also a * .v file generated in codegentemp folder that contains the verilog code generated. 


            ~ srim