The Component Author Guide will show you how to create components using Verilog. This also speaks about the use of Datapath tool for component creation.
If you want to get started quickly, you can watch component creation using Verilog training video which can be downloaded from here http://www.cypress.com/?rID=40330
The code which you have posted in your previous comment is that of a task which acts as an XNOR Gate. The output "c" is high when the inputs, "a" and "b" are same. Else, the output is low.
Thanks for the reply.
I can see what that Verilog example does, but what I don't understand is why they wrote it that way. Why didn't they do this instead?
task add; // task definition
input a, b; // two input argument ports
output c; // one output argument port
if (a == b)
c = 1;
c = 0;
And, lastly. Is there some teaching resource which explains these kinds of design decisions.