5 Replies Latest reply on Feb 9, 2012 3:37 PM by krishna.chaitanya

    OE_n significance in CY7C1370D  SRAM

    krishna.chaitanya

       Hi

         

      I'm working on interfacing cy7c1370d with spartan 6 fpga. In the data sheet its specified that the output buffers are tristated automaticaly during the 2nd cycle of the write operation where the data is presented on the DQ lines . but in the switching waveform of the datasheet at one clock transition the OE_n is high for half of the clock duration . Do i need to do the same while writing into the device ? please help...