DQs/DQPs are tristated when --> (WE# enabled) OR (Chip is disabled) OR (OE# is disable)
So, DQs/DQPs are automatically tristated during the data portion of a write cycle regardless of the state of OE#
you can have proper OE# level during the status change, like when status changes from read to write then OE# should be disable and from write to read OE# should be enable.
You can use both option according to your convenience.
I hope this clarifies your concern.
Thank you prit for the reply
and i had another problem in using the VHDL and Verilog model for CY7C1370D , when I initialize the memory as a component and instantiate it in my program with all the necessary inputs in xilinx , it gives an error in the model for illegal declaration in the sensitivity list for the clock validation process , can you suggest me how should i simulate the model without these errors ?
Could you please be more specific about the error.
problem with verilog model :'force statement not supported for synthesis'
and for VHDL model it says : Line 231: Illegal name on the sensitivity list
the line 231 is : WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH);
These are the problems im facing while trying to use the model. ANy help is highly appreciated .
I think i Found the problem i was trying to syntehsize the model which is a wrong thing to do . It has to be used in the simulation (testbench) .