VC-3 and its associated interrupt

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Anonymous
Not applicable

 hi developers,

   
   

                       i was going through a wonderfully written application note AN32200 ( http://www.cypress.com/?docID=27337 ), on clocks and global resources. the description of VC3 clock source states( If i have understood it correctly) that VC3's every positive edge can be used as an interrupt. is that so.? if so how can we eneable or disable this interrupt in the designer IDE. i couldn't find any options like "VC3 interrupt enable/disable". 

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Bob_Marlowe
Level 10
Level 10
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The application note says:

   

Interrupts can be enabled to occur on each rising edge of VC3. These interrupts are enabled by setting bit 7 of the INT_MSK0 register. The

   

   

boot.tpl file must also be modified to add code to the VC3 vector in the interrupt vector table. The boot.tpl file is the template file used to generate boot.asm

   

this is the usual way to gain acce3ss to the interrupt-system in PSoC1.

   

Do not forget (when using C) to  declare your interrupt-routine with the appropiate #pragma definition and avoid calling other C-functions within that routine.

   

 

   

Happy coding

   

Bob

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

   

The application note says:

   

Interrupts can be enabled to occur on each rising edge of VC3. These interrupts are enabled by setting bit 7 of the INT_MSK0 register. The

   

   

boot.tpl file must also be modified to add code to the VC3 vector in the interrupt vector table. The boot.tpl file is the template file used to generate boot.asm

   

this is the usual way to gain acce3ss to the interrupt-system in PSoC1.

   

Do not forget (when using C) to  declare your interrupt-routine with the appropiate #pragma definition and avoid calling other C-functions within that routine.

   

 

   

Happy coding

   

Bob

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Anonymous
Not applicable

 bob, 

   

    thanks for the clarification. you mean to say  that interrupts corresponding to any internal module, for instance the timer overflow interrupt can be responded to in sync with VC3 rising edge by using appropriate #pragma directive, even though they actually occured before the VC3 edge occurs.right?

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

No, negative. That has nothing to do with sync of two signals/interrupst.

   

And the #pragma directive I was referring to tells the compiler what C-procedures are interrupt handlers (which handle saaving and restoring registers automatically).

   

In the named assembly-template are clearly marked places to insert LCALL-instructions for handling the corresponding interrupt, one of them is for a VC3 interrupt.

   

 

   

Bob

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