9 Replies Latest reply on Mar 15, 2012 1:47 AM by anandsrinivasana_

    FX2LP Slave FIFO Manual Out without the involvement of the Host PC, is this possible?

      I am trying to establish a communication channel between FX2LP and a FPGA using the Slave FIFO. I use EP4 for this purpose. The configuration is as follows:


      1. EP2, Auto Out, 512 bytes, bulk, triple buffered


      2. EP4, Manual Out, 512 bytes, bulk, double buffered


      3. EP6, Auto In, 512 bytes, bulk, triple buffered


      4. EP8, not used.


      The slave FIFO is 16-bit wide. I am trying to send 52 bytes of data from FX2LP to FPGA via EP4 without the involvement of the host PC. Is that possible? I have tried many ways of coding, but the Empty flag of EP4, i.e. (EP2468STAT & 0x04) or (EP24FIFOFLAGS & 0x20), was still asserted after 52 bytes of data had been written into EP4 by FX2LP.  As the FPGA had not been programmed to read data from EP4 yet, I would assume the Empty flag of EP4 would have gone off after one packat of data had been sent. So do I have to send the 52 bytes of data from the host PC?


      Thanks for any help in advance.