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Hi!
Here is a quite strange phenomenon which has been confusing me...
Things goes like this:
I feed the Slave FIFO with the external logic FPGA when a key is pressed.
Before the key is pressed down, FIFO_FULL_FLAG is high and FIFO_EMPTY_FLAG is low.
After the key is pressed, FIFO_FULL_FLAG is low and FIFO_EMPTY_FLAG is high. Obviously,it is normal.
However, when I access the data in the SLAVE FIFO through the control pannel, the FIFO_FULL_FLAG remains low and the FIFO_EMPTY_FLAG remains high. \
How can i fix it?
Solved! Go to Solution.
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Hi,
Please post your code. I would like to take a look into the same.
Regards,
Gayathri
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Hi,
Please post your code. I would like to take a look into the same.
Regards,
Gayathri
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Hi,
Please check your Endpoint buffer configuration whether its valid or not. For more information on valid endpoint configurations go through section 1.17 EZ USB endpoint Buffers of TRM.
Thanks
Prajith
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I used the asynchronous mode. And the fequency of pusle clock of SLWR was too high.
It seems that there is liminition for the frequnency of SLWR...
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