4 Replies Latest reply on Jan 27, 2014 1:17 AM by prajithc_

    Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.



      Here is a quite strange phenomenon which has been confusing me...


      Things goes like this:


      I feed the Slave FIFO with the external logic FPGA when a key is pressed.


      Before the key is pressed down,  FIFO_FULL_FLAG is high and FIFO_EMPTY_FLAG is low.


      After the key is pressed,  FIFO_FULL_FLAG is low and FIFO_EMPTY_FLAG is high.  Obviously,it is normal. 


      However, when I access the data in the SLAVE FIFO through the control pannel, the FIFO_FULL_FLAG remains low and the  FIFO_EMPTY_FLAG remains high.          \


      How can i fix it?