hi,thank you for your reply,my FPGA system clock is 50MHz,the FPGA work on it and my PCLK is it too,is that OK?
the SDK1.0.1 you can find it in this website,hope it won't take you much time to find it,
I don't quite get your point? you say the problem is my FPGA control signals make no difference to the FX3 because of the VIO voltage domain ,but I can work asynchronous slave fifo well,so I thing my problem maybe stay at the PCLK or the timing sequence? maybe i didn't catch you point,i will check the VIO voltage first.
can you tell us what is your problem?
the important signal is ?