4 Replies Latest reply on Apr 11, 2012 7:46 AM by shiv.dhruw

    Problem in reading data from EZUSB-LX2LP

    shiv.dhruw

      I am new to this field, so just learning........

         

      Below is the firmware code  please correct it if any mistake is there.

         

               

         

      void TD_Init( void )

         

      { // Called once at startup

         

       

         

        CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

         

        /*1 0010  48MHz, CLKOUT pin driven*/

         

       

         

        IFCONFIG = 0xCB; // for async?  IFCONFIG

         

        /*1100 1111  Internal default clk, 48MHz,async , slave fifo interface*/

         

       

         

         

         

        SYNCDELAY;                    // see TRM section 15.14

         

        EP2CFG = 0xA2;                // BUF[1:0]=10 for 2x buffering

         

        /*Endpoint 2 Configuration 1010 0010*/

         

        //bit 7 1 to activate an end point

         

        //bit 6 0 OUT

         

        //bit 5 1

         

        //bit 4 0  Bulk(default)

         

        //bit 3 0 512 bytes

         

        //bit 2 0

         

        //bit 1 1  double

         

        //bit 0 0

         

       

         

        // EP6 512 BULK IN 2x

         

        SYNCDELAY;                    //

         

        EP6CFG = 0xE2;                // BUF[1:0]=10 for 2x buffering

         

        /*1110 0010*/

         

        //bit 7 1 to activate an end point

         

        //bit 6 1 IN

         

        //bit 5 1

         

        //bit 4 0  Bulk(default)

         

        //bit 3 0 512 bytes

         

        //bit 2 0

         

        //bit 1 1  double

         

        //bit 0 0

         

       

         

        // EP4 and EP8 are not used in this implementation...

         

        SYNCDELAY;                    //

         

        EP4CFG = 0x20;                // clear valid bit 10 0000

         

        //bit 7 0 to deactivate an end point

         

        //bit 6 0 OUT

         

        //bit 5 1

         

        //bit 4 0  Bulk(default)

         

        //bit 3 0 512 bytes

         

        //bit 2 0

         

        //bit 1 0  quad

         

        //bit 0 0

         

        SYNCDELAY;                    //

         

        EP8CFG = 0x60;                // clear valid bit 0110 0000

         

        //bit 7 0 to deactivate an end point

         

        //bit 6 1 IN

         

        //bit 5 1

         

        //bit 4 0  Bulk(default)

         

        //bit 3 0 512 bytes

         

        //bit 2 0

         

        //bit 1 0  quad

         

        //bit 0 0

         

       

         

        SYNCDELAY;

         

        FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

         

        SYNCDELAY;                    // see TRM section 15.14

         

        FIFORESET = 0x02;             // reset, FIFO 2

         

        SYNCDELAY;                    //

         

        FIFORESET = 0x04;             // reset, FIFO 4

         

        SYNCDELAY;                    //

         

        FIFORESET = 0x06;             // reset, FIFO 6

         

        SYNCDELAY;                    //

         

        FIFORESET = 0x08;             // reset, FIFO 8

         

        SYNCDELAY;                    //

         

        FIFORESET = 0x00;             // deactivate NAK-ALL

         

       

         

       

         

        // handle the case where we were already in AUTO mode...

         

        // ...for example: back to back firmware downloads...

         

        SYNCDELAY;                    //

         

        EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=1

         

       

         

       

         

        // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

         

       

         

        SYNCDELAY;                    //

         

        EP2FIFOCFG = 0x11;            // AUTOOUT=1, WORDWIDE=1  0001 0001 (16 bit)

         

        //bit 6 0  flag for synch fifo

         

        //bit 5 0  flag for synch fifo

         

        //bit 4 1 AUTOOUT buffer is automatically and instantaneously committed to the endpoint FIFO

         

        //bit 3 0 

         

        //bit 2 0

         

        //bit 1 0  

         

        //bit 0 1

         

       

         

        SYNCDELAY;                    //

         

        EP6FIFOCFG = 0x0D;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1  0000 1101(16 bit)

         

        //bit 6 0  flag for synch fifo

         

        //bit 5 0  flag for synch fifo

         

        //bit 4 0 

         

        //bit 3 1 AUTOIN buffer is automatically and instantaneously committed to the endpoint FIFO

         

        //bit 2 1 a zero length packet will be sent when PKTEND is activated

         

        //bit 1 0  

         

        //bit 0 0

         

        SYNCDELAY;

         

       

         

        PINFLAGSAB = 0xE0;                                          // FLAGA - indexed, FLAGB - EP6FF  1110 0000

         

        //bit 7 1  FLAGB3

         

        //bit 6 1  FLAGB2

         

        //bit 5 1  FLAGB1          (A8 priority 11 indicate Full)

         

        //bit 4 0  

         

        //bit 3 0 

         

        //bit 2 0

         

        //bit 1 0  

         

        //bit 0 0

         

        SYNCDELAY;

         

        PINFLAGSCD = 0x08;                                          // FLAGC - EP2EF, FLAGD - indexed  0000 1000

         

        //bit 7 0 

         

        //bit 6 0 

         

        //bit 5 0

         

        //bit 4 0  

         

        //bit 3 1  FLAGC3 - EP2EF (A0 priority 9 indicate Full )

         

        //bit 2 0

         

        //bit 1 0  

         

        //bit 0 0

         

        SYNCDELAY;

         

      }

         

       

         

      Above is the code for 16 bit Slave FIFO Interface, asynchronus mode.

         

       

         

      For testing firmware, I am using Bulk loop program to send and receive data. And loop back  I am doing from 32 bit Atmel AVR micro controller at other end.

         

       While I send data through bulk loop program it is received properly at Atmel controller. But when I send data from Atmel (or write data from Atmel into the slave fifo ) data is coming properly at cypress chip(I checked through digital osciloscope) but the bulk loop program not showing any data.

         

      Please have a look at firmware code for any mistake.

         


      Thanks in advance……